Method of forming a MIM capacitor
View Patent ↗An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the memory region than in the logic region.
1. A method of forming an embedded DRAM system including DRAM cells and logic transistors on a single substrate, each of the DRAM cells having a metal insulator-metal (MIM) capacitor, the method comprising:
providing a first dielectric layer above the substrate;
selectively etching an opening in the first dielectric layer to form a MIM capacitor within a memory region;
increasing the thickness of the first dielectric layer, and then planarizing the first dielectric layer;
forming a hole through said planarized layer to form a coupling via that is coupled to the MIM capacitor;
forming a second dielectric layer above said coupling via;
simultaneously forming via openings in the memory and logic regions after the coupling via is formed;
filling said via openings with a conductive material to form interconnect portions having a lower resistivity than said coupling via.
2. The method of claim 1 , wherein a dual damascene process is used to fill the via openings that are simultaneously formed after formation of the coupling via in the embedded DRAM system.
3. A method of forming an embedded DRAM system including DRAM cells and logic transistors on a single substrate, each of the DRAM cells having a metal-insulator-metal {MIM) capacitor, the method comprising:
forming an insulating layer above the substrate;
forming a first metal layer in one region of the DRAM system;
providing a first dielectric layer above the DRAM system;
forming a MIM capacitor in the first dielectric layer after the first metal layer has been formed;
providing a second dielectric layer above the first dielectric layer;
forming a coupling via in the second dielectric layer above the MIM capacitor;
simultaneously forming a second via in the memory region and a third via in a logic region;
providing a third dielectric layer;
filling the coupling via with a conductive material having a different resistivity than the conductive material provided in the second and third vias.
4. The method of claim 3 , wherein a dual damascene process is used to fill the vias that are simultaneously formed after the coupling via.
5. A method of forming an embedded DRAM system including DRAM cells and logic transistors on a single substrate, each of the DRAM cells having a metal-insulator-metal (MIM) capacitor, the method comprising:
forming an insulating layer above the substrate;
forming a first metal layer in one region of the DRAM system above the insulating layer;
providing a first dielectric layer above the first metal layer;
forming a MIM capacitor in a memory region after the first metal layer has been formed;
providing a second dielectric layer above the first dielectric layer;
forming a coupling via in the second dielectric layer that is coupled to the MIM capacitor;
simultaneously forming a first set of vias in the first and second dielectric layer;
forming interconnects in the DRAM system by filling the first set vias with a conductive material having a lower resistivity than the conductive material within the coupling via.
6. The method of claim 5 , wherein the first metal layer is formed in only the logic region.
7. The method of claim 5 , further comprising forming a second metal layer that electrically couples to the interconnects in the memory region and logic region.
8. The method of claim 5 , wherein a dual damascene process is used to fill the first set of vias.
9. The method of claim 5 , wherein the MIM capacitor has a top electrode that is not formed from the second metal layer.