Semiconductor chip layout with staggered Tx and Tx data lines
View Patent ↗A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
1. An integrated circuit device comprising:
a first semiconductor die comprising;
a central axis dividing the first semiconductor die into a first portion and a second portion;
a first serial interface located approximately at the central axis, the serial interface comprising a first transmitter port and a first receiver port;
a first plurality of Tx data lines connected to the first transmitter port and extending away from the central axis, at least one Tx data line of the first plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die; and
a first plurality of Rx data lines connected to the first receiver port and extending away from the central axis, at least one Rx data line of the first plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die.
2. The integrated circuit device of claim 1 , wherein the first semiconductor die further comprises:
a SERDES located approximately at the central axis and coupled to both the plurality of receiver ports and the plurality of transmitter ports of the first serial interface.
3. The integrated circuit device of claim 2 , wherein the SERDES comprises a width perpendicular to the central axis and defining an overlap region extending along the central axis, and wherein the at least one Tx data line is contained within the first portion and the overlap region, and wherein the at least one Rx data line is contained within the second portion and the overlap region.
4. The integrated circuit device of claim 2 , wherein the Tx port of the first serial interface is separated from the Rx port of the first serial interface by the SERDES.
5. The integrated circuit device of claim 1 , wherein the first plurality of Tx lines are separated from the first plurality of Rx lines to inhibit cross-coupling.
6. The integrated circuit device of claim 1 further comprising;
a second serial interface located approximately at the central axis, the serial interface comprising a second transmitter port and a second receiver port;
a second plurality of Tx data lines connected to the second transmitter port and extending away from the central axis, at least one Tx data line of the second plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die; and
a second plurality of Rx data lines connected to the second receiver port and extending away from the central axis, at least one Rx data line of the second plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die.
7. The integrated circuit device of claim 6 , wherein the first serial interface is separated from the second serial interface by the SERDES.
8. The integrated circuit device of claim 6 , wherein the Tx port of the first serial interface is adjacent to the Rx port of the second serial interface.
9. The integrated circuit device of claim 6 , wherein the Tx port of the first serial interface is adjacent to the Tx port of the second serial interface.
10. The integrated circuit device of claim 1 , further comprising:
a first layer, wherein the first semiconductor die is mounted to the first substrate and includes a first edge, a second edge, and a serial interface including a plurality of Tx ports and a plurality of RX ports;
a second semiconductor die mounted to the first substrate and having a first edge, a second edge, and a serial interface including a plurality of Tx ports and a plurality of Rx ports; and
a second layer mounted to the first substrate, wherein the first plurality of data lines pass through the first substrate, and wherein the second plurality of data lines pass through the second substrate.
11. An integrated circuit device comprising:
a first semiconductor die comprising;
a central axis dividing the first semiconductor die into a first portion and a second portion;
a serial interface located approximately at the central axis, the serial interface comprising a first transmitter port and a first receiver port;
a first plurality of Tx data lines connected to the first transmitter port and extending away from the central axis, at least one Tx data line of the first plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die;
a first plurality of Rx data lines connected to the first receiver port and extending away from the central axis, at least one Rx data line of the first plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die; and
a SERDES located approximately at the central axis and coupled to both the first receiver port and the first transmitter port of the first serial interface.
12. The integrated circuit device of claim 11 , wherein the SERDES comprises a width perpendicular to the central axis and defining an overlap region extending along the central axis, and wherein the at least one Tx data line is contained within the first portion and the overlap region, and wherein the at least one Rx data line is contained within the second portion and the overlap region.
13. The integrated circuit device of claim 11 , wherein the Tx port of the first serial interface is separated from the Rx port of the first serial interface by the SERDES.
14. The integrated circuit device of claim 11 , wherein the first plurality of Tx lines are separated from the first plurality of Rx lines to inhibit cross-coupling.
15. The integrated circuit device of claim 11 further comprising;
a second serial interface located approximately at the central axis, the serial interface comprising a second transmitter port and a second receiver port;
a second plurality of Tx data lines connected to the second transmitter port and extending away from the central axis, at least one Tx data line of the second plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die; and
a second plurality of Rx data lines connected to the second receiver port and extending away from the central axis, at least one Rx data line of the second plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die.
16. The integrated circuit device of claim 15 , wherein the first serial interface is separated from the second serial interface by the SERDES.
17. The integrated circuit device of claim 15 , wherein the Tx port of the first serial interface is adjacent to the Rx port of the second serial interface.
18. The integrated circuit device of claim 15 , wherein the Tx port of the first serial interface is adjacent to the Tx port of the second serial interface.
19. The integrated circuit device of claim 11 , further comprising:
a first layer, wherein the first semiconductor die is mounted to the first substrate and includes a first edge, a second edge, and a serial interface including a plurality of Tx ports and a plurality of RX ports;
a second semiconductor die mounted to the first substrate and having a first edge, a second edge, and a serial interface including a plurality of Tx ports and a plurality of Rx ports; and
a second layer mounted to the first substrate, wherein the first plurality of data lines pass through the first substrate, and wherein the second plurality of data lines pass through the second substrate.
20. An integrated circuit device comprising:
a first semiconductor die comprises:
a central axis dividing the first semiconductor die into a first portion and a second portion;
a first serial interface located approximately at the central axis, the first serial interface comprising a first transmitter port and a first receiver port;
a first plurality of Tx data lines connected to the first transmitter port and extending away from the central axis, at least one Tx data line of the first plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die;
a first plurality of Rx data lines connected to the first receiver port and extending away from the central axis, at least one Rx data line of the first plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die; and
a SERDES located approximately at the central axis and coupled to both the first receiver port and the first transmitter port of the serial interface, the SERDES comprising a width defining an overlap region extending away from the central axis, and wherein the at least one Tx data line is contained within the first portion and the overlap region, and wherein the at least one Rx data line is contained within the second portion and the overlap region.
21. The integrated circuit device of claim 20 , wherein the Tx port of the first serial interface is separated from the Rx port of the first serial interface by the SERDES.
22. The integrated circuit device of claim 20 , wherein the first plurality of Tx lines are separated from the first plurality of Rx lines to inhibit cross-coupling.
23. The integrated circuit device of claim 20 further comprising;
a second serial interface located approximately at the central axis, the serial interface comprising a second transmitter port and a second receiver port;
a second plurality of Tx data lines connected to the second transmitter port and extending away from the central axis, at least one Tx data line of the second plurality of Tx lines located in both the first portion and the second portion of the first semiconductor die; and
a second plurality of Rx data lines connected to the second receiver port and extending away from the central axis, at least one Rx data line of the second plurality of Rx lines located in both the first portion and the second portion of the first semiconductor die.
24. The integrated circuit device of claim 23 , wherein the first serial interface is separated from the second serial interface by the SERDES.
25. The integrated circuit device of claim 23 , wherein the Tx port of the first serial interface is adjacent to the Rx port of the second serial interface.
26. The integrated circuit device of claim 23 , wherein the Tx port of the first serial interface is adjacent to the Tx port of the second serial interface.
27. The integrated circuit device of claim 20 , further comprising:
a first layer, wherein the first semiconductor die is mounted to the first substrate and includes a first edge, a second edge, and a serial interface including a plurality of Tx ports and a plurality of RX ports;
a second semiconductor die mounted to the first substrate and having a first edge, a second edge, and a serial interface including a plurality of Tx ports and a plurality of Rx ports; and
a second layer mounted to the first substrate, wherein the first plurality of data lines pass through the first substrate, and wherein the second plurality of data lines pass through the second substrate.