Programmable partitionable counter
An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.
1. An integrated circuit device for receiving packets comprising:
a programmable partitionable counter comprising:
a first sub-counter having a width, the first sub-counter for counting a number of said packets; and
a second sub-counter having a width, the second sub-counter for counting bytes of said packets; and wherein:
said first sub-counter and said second sub-counter are configured to be incremented by a single command from said packet processor;
the programmable partitionable counter is configured to receive a partition offset size;
the partition offset size varies a first sub-counter size by adding the partition offset size to a nominal partition width; and
the partition offset size varies a second sub-counter size by subtracting the partition offset size from a nominal partition width.
2. The integrated circuit of claim 1 , wherein said the integrated circuit is a system-on-chip (SoC).
3. The integrated circuit of claim 1 , further comprising:
a logic unit configured as said programmable partitionable counter.
4. The integrated circuit of claim 3 , wherein said logic unit further comprises:
an error correcting code (ECC) module.
5. The integrated circuit of claim 1 , wherein a sum of the first sub-counter width and said second sub-counter width is a fixed quantity of bits.
6. The integrated circuit of claim 1 , wherein:
the width of the first sub-counter and the width of the second sub-counter both have a fixed size.
7. The integrated circuit of claim 1 , wherein:
the programmable partition counter is configured to perform a dual updating operation; and
the dual updating operation increments the first sub-counter for packets based on a receipt of a packet size of bytes used to update the second sub-counter.
8. The integrated circuit of claim 1 , further comprising:
an incrementer for incrementing said first counter; wherein
the incrementer is configured to increment the first sub-counter a programmable quantity of bits.
9. An integrated circuit device for receiving packets comprising:
a programmable partitionable counter comprising:
a first sub-counter having a width, the first sub-counter for counting a number of said packets; and
a second sub-counter, having a width, the second sub-counter for counting bytes of said packets, wherein said first sub-counter and said second sub-counter are configured to be incremented by a single command from said packet processor; and wherein
a size of said first sub-counter width and said second sub-counter width are configured to be programmably changed; and
the width of the partitions is stored on the IC;
the programmable partitionable counter is configured to receive a partition offset size;
the partition offset size varies a first sub-counter size by adding the partition offset size to a nominal partition width; and
the partition offset size varies a second sub-counter size by subtracting the partition offset size from a nominal partition width.
10. The integrated circuit of claim 9 , wherein said at least said first sub-counter does not receive any of said packets when said first sub-counter reaches its maximum value.
11. An integrated circuit device for receiving packets comprising:
a programmable partitionable counter comprising:
a first sub-counter having a partition, the first sub-counter for counting a number of said packets; and
a second sub-counter, having a partition, the second sub-counter for counting bytes of said packets, wherein said first sub-counter and said second sub-counter are configured to be incremented by a single command from said packet processor; and wherein
an entry value for said second sub-counter partition corresponds with an entry value for said first sub-counter partition,
the programmable partitionable counter is configured to receive a partition offset size;
the partition offset size varies a first sub-counter size by adding the partition offset size to a nominal partition width; and
the partition offset size varies a second sub-counter size by subtracting the partition offset size from a nominal partition width.
12. A data traffic governing system comprising:
a packet processor; and
an integrated circuit device comprising:
a programmable partitionable counter comprising:
a first sub-counter having a partition, the first sub-counter for counting a number of said packets; and
a second sub-counter having a partition, the second sub-counter for counting bytes of said packets, wherein said first sub-counter and said second sub-counter are configured to be incremented by a single command from said packet processor;
the programmable partitionable counter is configured to receive a partition offset size;
the partition offset size varies a first sub-counter size by adding the partition offset size to a nominal partition width; and
the partition offset size varies a second sub-counter size by subtracting the partition offset size from a nominal partition width.
13. The data traffic governing system of claim 12 , wherein said logic unit further comprises:
an error correction code module.
14. The data traffic governing system of claim 12 wherein at least one of said first sub-counter partition and said second sub-counter partition is 64 bits wide.
15. An integrated circuit device for receiving packets comprising:
a programmable partitionable counter wherein:
the counter is configured to be split into a plurality of partitioned sub-counters of two or greater;
a width of at least two of the sub-counters is configured to be programmably changed;
the width of the partitions is stored on the IC;
the programmable partitionable counter is configured to receive a partition offset size;
the partition offset size varies a first sub-counter size by adding the partition offset size to a nominal partition width; and
the partition offset size varies a second sub-counter size by subtracting the partition offset size from a nominal partition width.
16. The integrated circuit device of claim 15 , wherein:
at least two of the plurality of partitioned sub-counters operate separately from each other.
17. The integrated circuit device of claim 15 , wherein:
the plurality of partitioned sub-counters has a total fixed quantity of bits.
18. The integrated circuit device of claim 17 , wherein:
the fixed quantity of bits is 64 bits.
19. The integrated circuit device of claim 15 , wherein:
the partition size of at least one of the plurality of partitioned sub-counters is variable.
20. The integrated circuit device of claim 15 , wherein:
at least one of the sub-counters has a partition of 1 bit.
21. The integrated circuit device of claim 15 , wherein:
the programmable partitionable counter is configured to receive a partition offset size from a source external to the integrated circuit.
22. The integrated circuit device of claim 15 , wherein:
a first account/user has a given partition offset size of a given programmable partitionable counter;
a second account/user has a given partition offset size of a given programmable partitionable counter; and
the partition offset size of the first account/user is different from the partition offset size of the second account/user.
23. The integrated circuit device of claim 15 , wherein:
a plurality of different accounts/users has a same partition offset size of a respective given programmable partitionable counter.