Method and apparatus to encode and synchronize a serial interface

1. A method comprising:

synchronizing a master device with a slave device, wherein the master device comprises a semiconductor device and wherein synchronizing comprises:

transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, wherein the first synchronization marker data pattern includes a first subset of a plurality of data segments that includes a first data segment comprising:

a first encoded data element; and

one of:

a first frame header comprising a first header and a copy of the first header; and

a first transition header comprising the first header and an inverse of the first header;

receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern;

wherein each of the plurality of data segments comprises:

a corresponding encoded byte; and

one of:

a corresponding frame header comprising a corresponding header and a copy of the corresponding header; and

a corresponding transition header comprising the corresponding header and an inverse of the corresponding header, and

wherein every N th data segment of the plurality of data segments includes the corresponding frame header, wherein N is a predetermined periodic selection number.

2. The method of claim 1 , wherein the first encoded data element is encoded using a data scrambler.

3. The method of claim 1 , wherein transmitting and receiving the first and second synchronization marker data patterns is independent of transmission of the request and is independent of reception of the reply.

4. The method of claim 1 , wherein the second synchronization marker data pattern includes a second subset of the plurality of data segments including a second data segment comprising:

a second encoded data element; and

one of:

a second frame header comprising a second header and a copy of the second header; and

a second transition header comprising the second header and an inverse of the second header.

5. The method of claim 1 , wherein N has a value of 128.

6. The method of claim 1 , wherein the first serial interface is the same as the second serial interface.

7. The method of claim 1 , wherein the first serial interface is distinct from the second serial interface.

8. An apparatus comprising a master device that is a semiconductor device, the master device comprising:

an encoder to generate a first synchronization marker data pattern, wherein the first synchronization marker data pattern includes a first subset of a plurality of data segments, and wherein the first subset of the plurality of data segments includes a first data segment comprising:

a first encoded data element; and

one of:

a first frame header comprising a first header and a copy of the first header; and

a first transition header comprising the first header and an inverse of the first header;

wherein each of the first subset of the plurality of data segments comprises:

a corresponding encoded data element; and

one of:

a corresponding frame header comprising a corresponding header and a copy of the corresponding header; and

a corresponding transition header comprising the corresponding header and an inverse of the corresponding header;

wherein every Nth data segment of the first subset of the plurality of data segments includes the corresponding frame header, wherein N is a predetermined periodic selection number, and wherein each encoded data element is encoded using a data scrambler;

a transmitting interface to transmit, via a first serial interface, the first synchronization marker data pattern at a first time; and

a receiving interface to receive, via a second serial interface, a second synchronization marker data pattern at a second time from a slave device in response to the transmitted first synchronization marker data pattern;

wherein the master device is configured to synchronize with the slave device based at least in part on the first time and the second time.

9. The apparatus of claim 8 , wherein the second synchronization marker data pattern comprises a second subset of the plurality of data segments that includes a second data segment comprising:

a second encoded data element; and

one of:

a second frame header comprising a second header and a copy of the second header; and

a first transition header comprising the second header and an inverse of the second header.

10. The apparatus of claim 8 , wherein the first header is not larger than one bit.

11. The apparatus of claim 8 , wherein the data scrambler is a recoverable scrambler based on a polynomial.

12. An apparatus comprising a first slave device that comprises a semiconductor device, the first slave device comprising:

a receiving interface to receive, via a first serial interface, a first synchronization marker data pattern;

an encoder to generate a second synchronization marker data pattern in response to receipt by the first slave device of the first synchronization marker data pattern; and

a transmitting interface to transmit, via a second serial interface, the second synchronization marker data pattern;

wherein the second synchronization marker data pattern includes a plurality of data segments including a first data segment comprising:

a first encoded data element, wherein the first encoded data element is encoded using a data scrambler; and

one of:

a first frame header comprising a first header and a copy of the first header; and

a first transition header comprising the first header and an inverse of the first header

wherein each of the plurality of data segments comprises:

a corresponding encoded byte; and

one of:

a corresponding frame header comprising a corresponding header and a copy of the corresponding header; and

a corresponding transition header comprising the corresponding header and an inverse of the corresponding header, and

wherein every N th data segment of the plurality of data segments includes the corresponding frame header, wherein N is a predetermined periodic selection number.

13. The apparatus of claim 12 , wherein the first slave device is further configured to:

generate a third synchronization marker data pattern;

transmit the third synchronization marker data pattern at a first time;

receive a fourth synchronization marker data pattern at a second time from a second slave device in response to the transmitted third synchronization marker data pattern; and

synchronize the first slave device with the second slave device based at least on the first time and the second time.

14. The apparatus of claim 12 , wherein the first serial interface is a downstream serial interface and the second serial interface is an upstream serial interface, wherein the downstream serial interface is distinct from the upstream serial interface.

15. The apparatus of claim 12 , wherein the data scrambler is a recoverable scrambler based on a polynomial.

16. The apparatus of claim 12 , wherein the first header is not larger than one bit.

17. The apparatus of claim 12 , wherein N has a value of 128.

18. The apparatus of claim 12 , wherein the first header is not larger than one bit.

19. The method of claim 1 , further comprising determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.