Semiconductor device including a guard ring surrounding an inductor

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of insulating interlayers formed over said semiconductor substrate, and comprising a plurality of interconnect layers;

an inductor formed over said semiconductor substrate while placing at least one of said insulating interlayers in between;

a guard ring surrounding said inductor in a plan view, so as to isolate said inductor from other regions, said guard ring being connected to a first external substrate through a first pad that is applied with a reference potential; and

at least one transistor formed in said semiconductor substrate, said transistor being connected to a second external substrate through a second pad that is applied with the reference potential,

wherein an interconnect drawn out from the first pad and connected to the guard ring is electrically isolated from the second pad, and

wherein said guard ring comprises:

an annular impurity diffused layer provided in a surficial portion of said semiconductor substrate; and

an annular electro-conductor connected to said impurity diffused layer, and extended across said plurality of interconnect layers in said plurality of insulating interlayers, up to a layer having at least a height of the layer having said inductor provided therein.

2. The semiconductor device as claimed in claim 1 , wherein said electro-conductor of said guard ring is extended up to a layer having a level of height higher than that of the layer having said inductor provided therein.

3. The semiconductor device as claimed in claim 1 , wherein said guard ring is formed over said semiconductor substrate while placing a plurality of said insulating interlayers in between.

4. The semiconductor device as claimed in claim 1 , wherein said guard ring is applied with a ground potential as the reference potential.

5. The semiconductor device as claimed in claim 4 , wherein said at least one transistor comprises a plurality of transistors formed on said semiconductor substrate, said transistors being applied with the ground potential respectively, and

wherein over said semiconductor substrate, said guard ring is applied with the ground potential through a route different from a route through which said plurality of transistors are applied with said ground potential.

6. The semiconductor device as claimed in claim 1 , further comprising a buried insulating film provided in the surficial portion of said semiconductor substrate, in a region overlapping said inductor in the plan view.

7. The semiconductor device as claimed in claim 6 , wherein said buried insulating film is provided over an entire portion of the region overlapping said inductor in the plan view.

8. The semiconductor device as claimed in claim 6 , wherein said buried insulating film is provided in the region overlapping said inductor in the plan view, to allow a surface of said semiconductor substrate to expose like islands.

9. The semiconductor device as claimed in claim l, further comprising a plurality of dummy metals dispersively arranged in said insulating interlayers in the plan view,

wherein, in the plan view, a mean distance of every adjacent dummy metals is larger in an internal area of said guard ring than in an external area of said guard ring, and

wherein each of the dummy metals is isolated from each other.

10. The semiconductor device as claimed in claim 1 , wherein, in the plan view, said surficial portion of said semiconductor device overlaps other than the inductor.

11. The semiconductor device as claimed in claim 1 , wherein said surficial portion comprises a well disposed on said semiconductor substrate, said impurity diffused layer being disposed above a lower surface of the well.

12. The semiconductor device as claimed in claim 1 , wherein the first external substrate and the second external substrate are a self substrate.

13. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of insulating interlayers formed over said semiconductor substrate, and comprising a plurality of interconnect layers;

an inductor formed over said semiconductor substrate in one of said insulating interlayers; and

a guard ring surrounding said inductor in a plan view, to isolate said inductor from other regions,

wherein said guard ring comprises:

an annular impurity diffused layer provided in a well disposed on said semiconductor substrate; and

an annular electro-conductor connected to said impurity diffused layer, and extended across said plurality of interconnect layers in said plurality of insulating interlayers, up to a layer having a height higher than a height of the layer having said inductor provided therein.

14. The semiconductor device as claimed in claim 13 , further comprising:

at least one transistor formed in said semiconductor substrate,

wherein said guard ring is connected to an external substrate through a first pad and is applied with a reference potential,

wherein said transistor is connected to another external substrate through a second pad and is applied with the reference potential, and

wherein an interconnect drawn out from the first pad and connected to the guard ring is electrically isolated from the second pad.

15. The semiconductor device as claimed in claim 14 , wherein over said semiconductor substrate, said guard ring is applied with the reference potential through a route different from a route through which said at least one transistor is applied with said reference potential.

16. The semiconductor device as claimed in claim 13 , wherein, in the plan view, said well overlaps other than the inductor.

17. The semiconductor device as claimed in claim 13 , further comprising:

a buried insulating film provided in the well of said semiconductor substrate, in a region overlapping said inductor in the plan view.

18. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of insulating interlayers formed over said semiconductor substrate, and comprising a plurality of interconnect layers;

an inductor formed over said semiconductor substrate while placing at least one of said insulating interlayers in between;

a guard ring surrounding said inductor in a plan view, so as to isolate said inductor from other regions; and

a plurality of dummy metals dispersively arranged in said insulating interlayers in the plan view,

wherein, in the plan view, a mean distance between adjacent dummy metals is larger in an internal area of said guard ring than in an external area of said guard ring,

wherein said guard ring comprises:

an annular impurity diffused layer provided in a surficial portion of said semiconductor substrate; and

an annular electro-conductor connected to said impurity diffused layer, and extended across said plurality of interconnect layers in said plurality of insulating interlayers, up to a layer having at least a height of the layer having said inductor provided therein, and

wherein each of the dummy metals is isolated from each other.

19. The semiconductor device as claimed in claim 18 , wherein said guard ring is connected to a first external substrate through a first pad that is applied with a reference potential, and

wherein at least one transistor is formed in said semiconductor substrate, said transistor being connected to a second external substrate through a second pad that is applied with the reference potential,

wherein an interconnect drawn out from the first pad and connected to the guard ring is electrically isolated from the second pad.

20. The semiconductor device as claimed in claim 18 , wherein the dummy metals are isolated from said inductor and said guard ring.