Logic simulator and logic simulation method
A logic simulator includes a storage device and a simulator part. The storage device stores a signal duration delay file which associates first signal duration information indicating duration of an input signal supplied to a logic gate of a logic circuit with first element delay value information indicating a first element delay value. The simulator part extracts first element delay value information associated with the first signal duration information corresponding to second signal duration information indicating duration of an input signal supplied to the logic gate when a logic simulation is performed by referring the signal duration delay file, and performs the logic simulation of the logic circuit based on the extracted first element delay value information. By setting element delay value taking duration of an input signal into account, highly accurate logic simulation can be achieved.
1 . A logic simulator comprising:
a storage device configured to store a signal duration delay file which associates first signal duration information indicating duration of an input signal supplied to a logic gate of a logic circuit with first element delay value information indicating a first element delay value; and
a simulator part configured to extract first element delay value information associated with the first signal duration information corresponding to second signal duration information indicating duration of an input signal supplied to the logic gate when a logic simulation is performed by referring the signal duration delay file, and perform the logic simulation of the logic circuit based on the extracted first element delay value information.
2 . The logic simulator according to claim 1 , wherein in the signal duration delay file, the first signal duration information includes range information indicating a range of duration, and the first element delay value information includes a mathematical formula information indicating a mathematical formula for calculating the first element delay value based on the range information and the second signal duration information.
3 . The logic simulator according to claim 2 , wherein the signal duration delay file stores logic gate information specifying the logic gate and delay path information specifying which variation of input signal influences a variation of an output signal of the logic gate which are associated with the first signal duration information and the first element delay value information, and
the range information and the mathematical formula information are determined based on the logic gate information and the delay path information.
4 . The logic simulator according to claim 1 , wherein the storage device further stores a supply state delay file which associates supply state information indicating a supply state of an input signal supplied to the logic gate with second element delay information indicating a second element delay value, and
in the supply state delay file, the supply state information includes adjacent supply state information indicating supply state of an input signal of each of input terminals other than an input signal at a verification target input terminal among a plurality of input terminals included in the logic gate.
5 . The logic simulator according to claim 4 , wherein the supply state indicates a voltage of an input signal.
6 . The logic simulator according to claim 1 , wherein the signal duration delay file stores supply state information indicating a supply state of an input signal supplied to the logic gate associated with second element value information indicating a second element delay value, and further stores adjacent supply state information indicating supply state of an input signal of each of input terminals other than an input signal at a verification target input terminal among a plurality of input terminals included in the logic gate associated with the first signal duration information and the first element delay value information and the second element delay value.
7 . The logic simulator according to claim 6 , wherein the supply state indicates a voltage of an input signal.
8 . A logic simulation method comprising:
generating signal duration delay file which associates first signal duration information indicating duration of an input signal supplied to a logic gate of a logic circuit with first element delay value information indicating a first element delay value;
extracting first element delay value information associated with the first signal duration information corresponding to second signal duration information indicating duration of an input signal supplied to the logic gate when a logic simulation is performed by referring the signal duration delay file; and
performing the logic simulation of the logic circuit based on the extracted first element delay value information.
9 . The logic simulation method according to claim 8 , wherein the first signal duration information includes range information indicating a range of duration, and the first element delay value information includes a mathematical formula information indicating a mathematical formula for calculating the first element delay value based on the range information and the second signal duration information.
10 . The logic simulation method according to claim 9 , wherein the signal duration delay file stores logic gate information specifying the logic gate and delay path information specifying which variation of input signal influences a variation of an output signal of the logic gate which are associated with the first signal duration information and the first element delay value information, and
the range information and the mathematical formula information are determined based on the logic gate information and the delay path information.
11 . The logic simulation method according to claim 8 , further comprising:
generating a supply state delay file which associates supply state information indicating a supply state of an input signal supplied to the logic gate with second element delay information indicating a second element delay value,
wherein in the supply state delay file, the supply state information includes adjacent supply state information indicating supply state of an input signal of each of input terminals other than an input signal at a verification target input terminal among a plurality of input terminals included in the logic gate.
12 . The logic simulation method according to claim 11 , wherein the supply state indicates a voltage of an input signal.
13 . The logic simulation method according to claim 8 , further comprising:
associating supply state information indicating a supply state of an input signal supplied to the logic gate with second element value information indicating a second element delay value, and
generating adjacent supply state information indicating supply state of an input signal of each of input terminals other than an input signal at a verification target input terminal among a plurality of input terminals included in the logic gate associated with the first signal duration information and the first element delay value information and the second element delay value.
14 . The logic simulation method according to claim 13 , wherein the supply state indicates a voltage of an input signal.
15 . A computer program product embodied on a computer-readable medium and comprising code that, when executed, causes a computer to perform the logic simulation method according to claim 8 .