IP Library Patent Application 12294461
Patent Application
App. No. 12/294,461

Photo Sensor With Pinned Photodiode and Sub-Linear Response

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Quick Facts
Patent No.
US None
App. No.
12/294,461
Abstract

A photo sensor exhibiting low noise, low smear, low dark current and high dynamic range consists of a pinned (or buried) photodiode (PPD) with associated transfer gate (TG), a reset circuit ( 3 ) and a device (SL) with sub-linear voltage-to-current characteristic. The exposure cycle is started by reverse biasing the buried photodiode to its pinning potential and by setting the transfer gate (TG) to a non-zero skimming potential. Photo-generated charge carriers start to fill the buried photodiode; if illumination intensity is high, excessive photocharges are flowing over the transfer gate (TG) to the sensing node. Because of the sub-linear device (SL) connected to the sensing node, the voltage at the sensing node is a sub-linear function of the illumination intensity, and hence the dynamic range of the pixel is increased. The voltage at the sensing node (Se) is read four times, namely before exposure, with the spilled-over photocharge, after reset, and after the photocharge in the buried photodiode has been transferred to the sensing node. This allows correlated multiple sampling techniques to be employed for eliminating reset noise. Because of its compact size, the photo sensor can be employed in one- and two-dimensional image sensors fabricated with industry-standard CMOS or CCD technologies.

Claims (23)

1 . A photo sensor comprising a pinned photodiode (PPD) having a first and a second terminal and, between said first and said second terminal, having a pn-j unction for generating photoinduced charge carriers and a transfer gate (TG) to release said charge carriers to said first terminal characterized in that the photo sensor further comprises a sub-linear device (SL) for which a voltage drop over the sub-linear device (SL) depends in sub-linear fashion on a current through the device, wherein said sub-linear device (SL) is connected in series to said pinned photodiode (PPD), and a voltage generator for feeding a control voltage to said transfer gate (TG), wherein said voltage generator is adapted to generate a switch-on voltage (V-Ji) for removing all said charge carriers and a skimming voltage (Vg) lying between said switch-on voltage (Vp) and a voltage at said second terminal for partially opening said transfer gate (TG).

2 . The photo sensor of claim 1 wherein said sub-linear device (SL) is connected to said first terminal.

3 . The photo sensor device of claim 1 further comprising a reset circuit for setting said first terminal to a predefined potential.

4 . The photo sensor device of claim 3 further comprising a voltage sensor for measuring a measured voltage indicative of a voltage at said first terminal (D, a control circuit adapted to run repeti-tive measuring cycles, wherein each measuring cycle comprises a first and a second phase, wherein

a) in said first phase said control circuit issues a first reset command to said reset circuit ( 3 ), sets said voltage generator to generate said skimming voltage (Vg), and operates said voltage sensor to measure a first change of said measured voltage, and

b) in said second phase said control circuit operates said voltage generator ( 4 ) to issue said switch-on voltage (V<p) and operates said voltage sensor to measure a second change of said measured voltage.

5 . The photo sensor of claim 4 wherein, at a beginning of said second phase, said control circuit issues a second reset command to said reset circuit and wherein said second change of said measured voltage corresponds to a difference V 3 −V 4 with V 3 corresponding to a voltage after said second reset command and before generating said switch-on voltage (Vp) and V 4 corresponding to a voltage after generating said switch-on voltage-.

6 . The photo sensor of a claim 4 wherein said first change of said measured voltage corresponds to a difference V̂−V 2 with V]_corresponding to a voltage at a beginning of said first phase after issuing said first reset command and V 2 corresponding to a voltage at an end of said first phase.

7 . The photo sensor of claim 5 adapted to add said first change and second change of said measured voltage.

8 . The photo sensor of claim 3 wherein said reset circuit and said sub-linear device (SL) both comprise a common transistor in series to said pinned photodiode (PPD) and connected to a feed voltage, and wherein said photo sensor further comprises a control circuit adapted to

a) set said feed voltage to a reset voltage (VR) and applying a voltage pulse to a gate of said transistor for setting said first terminal to said predefined potential, and

b) set said feed voltage and said gate of said second transistor to a common voltage (Vĝ) below said reset voltage (VR) for operating said transistor as said sub-linear device (SL).

9 . The photo sensor of claim 1 wherein said sub-linear device (SL) is a diode or a diode-connected transistor.

10 . A photo sensor array comprising a plurality of photo sensors of.

11 . A method for operating a photo sensor comprising a pinned photodiode (PPD) having a first and a second terminal and, between said first and said second terminal, having a pn-junction for generating photoinduced charge carriers and a transfer gate (TG) to release said charge carriers to said first terminal characterized in said method comprises the following steps

in a first phase:

a) bringing said first terminal ( 1 ) to a predefined voltage (VR),

b) applying a skimming voltage (Vg) to said transfer gate (TG), which skimming voltage (Vg) lies between a switch-on voltage (Vp) of said transfer gate (TG) and a voltage at said second terminal for partially opening said transfer gate (TG),

c) feeding a current to said first terminal when a voltage at said first terminal falls below a given threshold, wherein said current increases super-linearly with a difference between the voltage at said first terminal and said threshold, and

in a second phase:

d) bringing said first terminal to said predefined voltage, and

e) applying the switch-on voltage (V-p) to said transfer gate (TG) for releasing all said charge carriers,

said method further comprising the steps of measuring a first and a second change of said voltage at said first terminal in said first phase and said second phase, respectively.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2009
From: CSEM CENTRE SUISSE D'ELECTRONIQUE ET DE MICROTECHNIQUE SA
To: CSEM CENTRE SUISSE D'ELECTRONIQUE ET DE MICROTECHNIQUE SA-RECHERCHE ET DEVELOPPEMENT
Reel/Frame 022839/0643 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2008
From: SEITZ, PETER; LUSTENBERGER, FELIX
To: CSEM CENTRE SUISSE D'ELECTRONIQUE ET DE MICROTECHNIQUE SA
Reel/Frame 021683/0499 →