Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor
View Patent ↗A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density.
1. A method of run-time reconfiguration, comprising the steps of:
writing reconfiguration bits into a first storage on a chip at a time of initial configuration; and
placing said reconfiguration bits into a second storage on the chip during run-time reconfiguration to configure one or more logic elements (LEs) and one or more switches to implement different logic functionalities and interconnections.
2. The method of claim 1 , wherein reconfiguration commences at one edge of a clock signal, followed by computation at another edge of the clock signal.
3. The method of claim 1 , comprising:
computing an ouput from at least one logic function implemented by at least one of the one or more LEs and at least one of the one or more switches; and
using the output for additional computation or storing the output for use by additional computation.
4. The method of claim 3 , wherein the at least one logic function, implemented by the at least one of the one or more LEs and at least one of the one or more switches, comprises a mapped configuration of the at least one of the one or more LEs, the at least one of the one or more switches, and one or more outputs.
5. The method of claim 3 , wherein the output is provided as input to at least one of the one or more LEs.
6. The method of claim 1 , wherein the one or more logic elements further comprise one or more look-up tables (LUTs).
7. The method of claim 6 , further comprising electrically coupling a LUT output storage to the one or more LUTs.
8. The method of claim 1 , wherein the one or more LEs further comprise a flip-flop.
9. The method of claim 3 , wherein at least one LE is configured to implement a m-variable Boolean function.
10. The method of claim 1 , wherein the first storage comprises carbon nanotube memory cells.
11. The method of claim 1 , wherein the first storage comprises phase change memory cells.
12. The method of claim 1 , wherein the first storage comprises magnoresistive memory cells.
13. The method of claim 1 , wherein the first storage comprises ferroelectric memory cells.
14. The method of claim 1 , wherein the second storage comprises a static random access memory (SRAM).
15. The method of claim 1 , further comprising:
loading a first group of reconfiguration bits, from said reconfiguration bits stored in the first storage, in a first portion of the second storage; and
utilizing a second portion of the second storage to perform computation.
16. A method of run-time reconfiguration, comprising the steps of:
writing reconfiguration bits into a first storage on a chip at a time of initial configuration; and
placing one or more of said reconfiguration bits into a second storage on the chip during run-time reconfiguration to configure one or more logic elements (LEs) and one or more switches to implement different logic functions.
17. The method of claim 16 , wherein reconfiguration commences at one edge of a clock signal, followed by computation at another edge of the clock signal.
18. The method of claim 16 , comprising:
computing an output from at least one logic function implemented by at least one of the one or more LEs and at least one of the one or more switches; and
using the output for additional computation or storing the output for use by additional computation.
19. The method of claim 18 , wherein the at least one logic function, implemented by the at least one of the one or more LEs and at least one of the one or more switches, comprises a mapped configuration of the at least one of the one or more LEs, the at least one of the one or more switches, and one or more outputs.
20. The method of claim 18 , wherein the output is provided as input to at least one of the one or more LEs.
21. The method of claim 16 , wherein the one or more logic elements further comprise one or more look-up tables (LUTs).
22. The method of claim 21 , further comprising electrically coupling a LUT output storage to the one or more LUTs.
23. The method of claim 16 , wherein the one or more LEs further comprise a flip-flop.
24. The method of claim 18 , wherein at least one LE is configured to implement a m-variable Boolean function.
25. The method of claim 16 , wherein the first storage comprises carbon nanotube memory cells.
26. The method of claim 16 , wherein the first storage comprises phase change memory cells.
27. The method of claim 16 , wherein the first storage comprises magnoresistive memory cells.
28. The method of claim 16 , wherein the first storage comprises ferroelectric memory cells.
29. The method of claim 16 , wherein the second storage comprises a static random access memory (SRAM).
30. The method of claim 16 , further comprising:
wherein placing one or more of said reconfiguration bits into the second storage on the chip during run-time reconfiguration comprises placing the one or more of said reconfiguration bits into a first portion of the second storage; and
utilizing a second portion of the second storage to perform a computation.