Configurable parallel computation of cyclic redundancy check (CRC) codes

1. An apparatus for implementing a cyclic redundancy check (CRC) error detection methodology to compute a CRC error detection code for data according to the methodology, the apparatus comprising:

computation means comprising a plurality of configurable elements, at least some of which comprise a data path circuit for receiving data and including an XOR gate providing an XOR function and a configurable device, the XOR gate receiving part of the data and using the received part of the data in the XOR function, at least one of the data path circuits configurable either to use the part of the data received by the circuit to compute a CRC error detection code by configuring the configurable device to output a signal resultant from the XOR function of the XOR gate or not to use the part of the data received by the circuit in the computation of the CRC error detection code by configuring the configurable device not to output a signal resultant from the XOR function of the XOR gate, the configurable elements operating in parallel to compute the CRC error detection code, and

configurator means which uses the CRC error detection methodology to determine a configuration of the computation means required to compute the CRC error detection code, and configures the computation means accordingly, wherein the configurator means is able to use each of a plurality of CRC error detection methodologies to determine a configuration of the computation means required for parallel computation of a CRC error detection code according to each of the methodologies, and the computation means is configurable to allow configuration thereof for parallel computation of each CRC error detection code.

2. The apparatus according to claim 1 , in which the configuration of at least some of the configurable elements is determined by the configurator means using one of the CRC error detection methodologies.

3. The apparatus according to claim 1 , in which for at least some of the configurable elements, each configurable element receives a part of the data and is configurable such that it either uses the part of the data in the computation of a CRC error detection code, or does not use the part of the data in the computation of the CRC error detection code.

4. The apparatus according to claim 1 , in which the configurable device outputs a signal which has been received by the device.

5. The apparatus according to claim 1 , in which at least some of the configurable elements each comprise a control-path circuit.

6. The apparatus according to claim 5 , in which at least some of the control-path circuits comprise a configurable device.

7. The apparatus according to claim 5 , in which at least some of the control-path circuits comprise a configuration register.

8. The apparatus according to claim 5 , in which for each of at least some of the configurable elements, the control-path circuit of an element controls the configuration of the data-path circuit of the element.

9. The apparatus according to claim 8 , in which for each of at least some of the configurable elements, the control-path circuit of an element controls the configuration of the configurable device of the data-path circuit of the element.

10. The apparatus according to 9 , in which for each of at least some of the configurable elements, the configurable device of the control-path circuit of an element controls the operation of the configuration register of the control-path circuit of the element, to control the configuration of the configurable device of the data-path circuit of the element.

11. The apparatus according to claim 1 , in which the configurable elements comprise an interconnected array of elements.

12. The apparatus according to claim 11 , in which for each row of the array of elements, the elements in a row are interconnected to collectively compute a part of a CRC error detection code.

13. The apparatus according to claim 11 , in which for each row of the array of elements, data received by each element in a row configured to use the data in the computation of a CRC error detection code is combined to compute a part of a CRC error detection code.

14. The apparatus according to claim 11 , in which for each row of the array, the elements in a row are interconnected to receive con figuration data from the configurator means.

15. The apparatus according to claim 11 , in which each column in the array of configurable elements receives a part of the data for parallel computation of a CRC error detection code.

16. The apparatus according to claim 11 , in which for each column in the array of elements, the elements in a column are interconnected to receive configuration control signals from the configurator means.

17. The apparatus according to claim 1 , in which the computation means receives the data in one or more blocks of data using two or more input devices.

18. The apparatus according to claim 17 , in which the size of the blocks received by the computation means is equal to or less than the number of input devices of the compulsion means.

19. The apparatus according to claim 18 , in which the or each input device which does not receive data is programmable to output a low signal.

20. The apparatus according to claim 1 , in which the computation means comprises one or more feedback devices at least some of which feed a part of a computed CRC error detection code hack into the computation means.

21. The apparatus according to claim 20 , in which the computation means computes a first CRC error detection code using a first block of the data, feeds the first CRC error detection code back into the computation means and combines it with a second block of the data, computes a second CRC error detection code using the combined second block of the data and the first CRC error detection code, continues this process until all of the data has been used to compute a final CRC error detection code, and outputs the final CRC error detection code.

22. The apparatus according to claim 20 , in which the computation means is programmable to receive data comprising a variable number of blocks, by programming appropriate devices of the input devices and programming appropriate devices of the feedback devices of the computation means.

23. The apparatus according to claim 1 , which is configurable to implement a plurality of CRC error detection methodologies, each using a CRC generator polynomial of a predetermined size.

24. The apparatus according to claim 23 , in which the configurator means uses a CRC generator polynomial of a CRC error detection methodology to calculate a CRC D matrix, winch determines the configuration of the computation means required to compute the CRC error detection code.

25. The apparatus according to claim 24 , in which the D matrix comprises an array of Os and 1s, and the positions of the 1s indicates the required location of configurable elements of the computation means which use the data in the computation of the CRC error detection code, and the positions of the Os indicates the required locations of configurable elements of the computation means which do not use the data in the computation of the CRC error detection code.

26. The apparatus according to claim 1 , which comprises a hardware device.

27. The apparatus according to claim 1 , which comprises part of a protocol processor.

28. A method of computing a cyclic redundancy check (CRC) error detection code for data according to a CRC error detection methodology, the method comprising:

providing an apparatus to implement a CRC error detection methodology and to compute a CRC error detection code, the apparatus comprising computation means comprising a plurality of configurable elements, at least some of which comprise a data path circuit for receiving data and including an XOR gate providing an XOR function and a configurable device, the XOR gate receiving part of the data and using the received part of the data in the XOR function, at least one of the data path circuits configurable either to use the part of the data received by the circuit to compute a CRC error detection code by configuring the configurable device to output a signal resultant from the XOR function of the XOR gate or not to use the part of the data received by the circuit in the computation of the CRC error detection code by configuring the configurable device not to output a signal resultant from the XOR function of the XOR gate, configurable elements operating in parallel to compute the CRC error detection code,

using, by a configurator means, CRC error detection methodology to determine a configuration of the computation means required to compute the CRC error detection code, and

configuring, by the configurator means, the computation means accordingly, wherein the configurator means is able to use each of a plurality of CRC error detection methodologies to determine a configuration of the computation means required for parallel computation of the CRC error detection code according to each of the methodologies, and the computation means is configurable to allow configuration thereof for parallel computation of each CRC error detection code.