Integrated circuit and assembly therewith
View Patent ↗An integrated circuit suitable for use at high frequencies and comprising a first capacitor having an input and an output, as well as a ground connection, wherein the capacitor is ESD-protected through an resistor between the capacitor output and the ground connection, which resistor has a resistance value that is sufficiently high so as to prevent any substantial influence on RF performance of the ground connection.
1. An integrated circuit arrangement comprising:
an integrated circuit located on the integrated circuit carrier including
a substrate;
an internal ground located below the substrate;
a capacitor located above bottom surface of the substrate and having an output node and an input node; and
a resistive element providing electrostatic discharge (ESD) protection for the capacitor by providing a first current path from the output node of the capacitor to the internal ground; and
an impedance element providing a second current path from the output node of the capacitor to the external ground, wherein the ratio of resistances between the first current path and the second current path is sufficient to substantially decouple the external ground from the internal ground at circuit-operating frequencies up to 900 MHz.
2. The integrated circuit arrangement of claim 1 , wherein the substrate has a resistivity and thickness tuned for the use of high quality inductors thereon.
3. The integrated circuit arrangement of claim 1 , wherein the substrate has a thickness of between 100 and 300 micrometers and a resistance of at least 0.5 kΩcm.
4. The integrated circuit arrangement of claim 1 , wherein the resistive element is connected to internal ground through a vertical interconnection within the substrate.
5. The integrated circuit arrangement of claim 1 , wherein the resistive element and the first current path are configured and arranged to provide ESD protection for the capacitor in the absence of the impedance element and the second current path and to decouple the internal ground.
6. The integrated circuit arrangement of claim 1 , further including
an integrated circuit carrier having
a carrier substrate;
at least one bond pad located on top of the substrate;
an inductor located within the carrier substrate and electrically connected to the at least one bond pad;
terminals located on a bottom of the carrier substrate; and
thermal vertical interconnections through the carrier substrate connected to one or more of the terminals;
an adhesive layer side bonded to the carrier substrate and to the substrate of the integrated circuit; and
a bond wire connecting the at least one bond pad to the integrated circuit, thereby providing the second current path.