Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device includes a silicon substrate; an N-channel field-effect transistor including a first gate insulating film on the silicon substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and a P-channel field-effect transistor including a second gate insulating film on the silicon substrate, a second gate electrode on the second gate insulating film and a second source/drain region. Each of the first and second gate electrodes includes a crystallized nickel silicide region containing an impurity element, the crystallized nickel silicide region being contact with the first or second gate insulating film, and a barrier layer region in an upper portion including an upper surface of the gate electrode, the barrier layer region containing an Ni diffusion-preventing element higher in concentration than that of a lower portion below the upper portion.
1. A semiconductor device comprising:
a silicon substrate;
an N-channel field-effect transistor including a first gate insulating film on said silicon substrate, a first gate electrode on said first gate insulating film, and a first source/drain region; and
a P-channel field-effect transistor including a second gate insulating film on said silicon substrate, a second gate electrode on said second gate insulating film, and a second source/drain region;
wherein each of said first and second gate electrodes comprises:
a crystallized nickel silicide region containing an impurity element, the crystallized nickel silicide region being contact with the first or second gate insulating film; and
a barrier layer region in an upper portion including an upper surface of said gate electrode, the barrier layer region containing an Ni diffusion-preventing element higher in concentration than that of a lower portion below the upper portion.
2. The semiconductor device according to claim 1 , wherein said Ni diffusion-preventing element is at least either one of a nitrogen atom and an oxygen atom.
3. The semiconductor device according to claim 1 , wherein the concentration of the Ni diffusion-preventing element of said barrier layer region is 0.1 to 10 atom %.
4. The semiconductor device according to claim 1 , wherein the thickness of said barrier layer region in a direction perpendicular to said silicon substrate is 1 to 10 nm.
5. The semiconductor device according to claim 1 ,
wherein said crystallized nickel silicide region of said first gate electrode contains an n-type impurity, and
said crystallized nickel silicide region of said second gate electrode contains a p-type impurity and has the same nickel silicide composition as said crystallized nickel silicide region of said first gate electrode.
6. The semiconductor device according to claim 1 , wherein a silicide composing each of said crystallized nickel silicide regions has a composition represented as Ni x Si 1-x (0.2≦x<0.4).
7. The semiconductor device according to claim 1 , wherein a silicide composing each of said crystallized nickel silicide regions includes an NiSi 2 crystal phase.
8. The semiconductor device according to claim 1 ,
wherein said first gate electrode includes, in a portion contact with said first gate insulating film, a region containing an n-type impurity higher in concentration than that of an upper portion above the region and
said second gate electrode includes, in a portion contact with said second gate insulating film, a region containing a p-type impurity higher in concentration than that of an upper portion above the region.
9. The semiconductor device according to claim 1 ,
wherein said first gate electrode includes, in a portion contact with said first gate insulating film, a region having an n-type impurity concentration of 1×10 20 cm −3 or higher and
said second gate electrode includes, in a portion contact with said second gate insulating film, a region having an p-type impurity concentration of 1×10 20 cm −3 or higher.
10. The semiconductor device according to claim 1 , wherein each of said first and second gate insulating films includes either one of a silicon dioxide film, a silicon oxynitride film and a silicon nitride film, the film being contact with said first or second gate electrode.
11. A method for manufacturing a semiconductor device as recited in claim 1 , comprising:
preparing a silicon substrate including a p-type active region and an n-type active region;
forming an insulating film for first and second gate insulating films on said silicon substrate;
forming a silicon film for gate electrodes on said insulating film;
doping an n-type impurity into said silicon film for gate electrodes in a region where an N-channel field-effect transistor is to be formed;
doping a p-type impurity into said silicon film for gate electrodes in a region where a P-channel field-effect transistor is to be formed;
processing said silicon film for gate electrodes to form a gate pattern;
forming a first source/drain region in a region where the N-channel field-effect transistor is to be formed;
forming a second source/drain region in a region where the P-channel field-effect transistor is to be formed;
forming an interlayer insulating film over said gate pattern;
removing an upper-layer portion of said interlayer insulating film such that said gate pattern is exposed;
forming a nickel film on said exposed gate pattern;
irradiating an Ni diffusion-preventing element to an entire surface of said nickel film;
forming first and second gate electrodes by performing a heat treatment and thereby siliciding said gate pattern; and
removing an unsilicided excess nickel of said nickel film.
12. The method for manufacturing a semiconductor device according to claim 11 , wherein said Ni diffusion-preventing element is at least either one of a nitrogen atom and an oxygen atom.
13. The method for manufacturing a semiconductor device according to claim 11 , wherein the irradiation of said Ni diffusion-preventing element is performed using a plasma irradiation method or an ion implantation method.
14. The semiconductor device according to claim 2 , wherein the concentration of the Ni diffusion-preventing element of said barrier layer region is 0.1 to 10 atom %.
15. The semiconductor device according to claim 2 , wherein the thickness of said barrier layer region in a direction perpendicular to said silicon substrate is 1 to 10 nm.
16. The semiconductor device according to claim 3 , wherein the thickness of said barrier layer region in a direction perpendicular to said silicon substrate is 1 to 10 nm.
17. The semiconductor device according to claim 2 , wherein said crystallized nickel silicide region of said first gate electrode contains an n-type impurity, and
said crystallized nickel silicide region of said second gate electrode contains a p-type impurity and has the same nickel silicide composition as said crystallized nickel silicide region of said first gate electrode.
18. The semiconductor device according to claim 3 , wherein said crystallized nickel silicide region of said first gate electrode contains an n-type impurity, and
said crystallized nickel silicide region of said second gate electrode contains a p-type impurity and has the same nickel silicide composition as said crystallized nickel silicide region of said first gate electrode.
19. The semiconductor device according to claim 3 , wherein said crystallized nickel silicide region of said first gate electrode contains an n-type impurity, and
said crystallized nickel silicide region of said second gate electrode contains a p-type impurity and has the same nickel silicide composition as said crystallized nickel silicide region of said first gate electrode.
20. The semiconductor device according to claim 2 , wherein a silicide composing each of said crystallized nickel silicide regions has a composition represented as Ni x Si 1i-x (0.2≦x<0.4).