Termination circuit

1. A termination circuit comprising:

an external connection terminal;

a terminating resistor circuit that includes a plurality of resistance elements, wherein connections of the plurality of resistance elements to the external connection terminal are capable of being turned on and off; and

a control circuit for exercising control so as to temporally stagger on/off timings of respective ones of said plurality of resistance elements,

wherein said termination circuit has a plurality of transistors for turning the connections of said plurality of resistance elements to said external terminal on and off,

wherein said control circuit controls timings at which respective ones of said plurality of transistors are turned on and off by changing slew rates of respective ones of control signals supplied to said plurality of transistors,

wherein said control circuit has driving circuits, each of which includes a plurality of driving transistors, for driving respective ones of said plurality of transistors; and

each of said driving circuits varies the slew rate by changing the number of the plurality of driving circuits that are activated.

2. The circuit according to claim 1 , wherein said control circuit controls timings at which respective ones of said plurality of transistors are turned on and off by delaying operation of respective ones of said transistors.

3. A buffer circuit equipped with terminating resistors, comprising:

the termination circuit set forth in claim 1 ; and

an input circuit, output circuit or input/output circuit connected to said external connection terminal,

wherein said control circuit outputs an enable signal to said input circuit, output circuit or input/output circuit after on/off control in each of said plurality of resistance elements is completed.

4. A semiconductor integrated circuit device having the buffer circuit equipped with terminating resistors set forth in claim 3 .

5. A semiconductor integrated circuit device having the termination circuit set forth in claim 1 .

6. The termination circuit according to claim 1 , wherein the control circuit avoids an overlap of switching of on/off timings among each one of the plurality of resistance elements.

7. A termination circuit comprising:

a control circuit providing a control signal;

a terminating resistor circuit including a plurality of resistance elements, each one of the plurality of resistance elements being selectively turned on and off according to the control signal from the control circuit; and

an external connection terminal being connected to the terminating resistor circuit,

wherein the control circuit provides the control signal to delay on and off timings of respective ones of said plurality of resistance elements,

wherein the termination circuit includes a plurality of transistors for switching connections of the plurality of resistance elements to the external terminal on and off,

wherein the control circuit controls timings at which respective ones of said plurality of transistors are turned on and off by changing slew rates of respective ones of control signals supplied to said plurality of transistors,

wherein said control circuit includes driving circuits, each of which includes a plurality of driving transistors, for driving respective ones of said plurality of transistors, and

wherein each of said driving circuits varies the slew rate by changing the number of the plurality of driving circuits that are activated.

8. The circuit according to claim 7 , wherein the termination circuit includes a plurality of switches for turning connections of the plurality of resistance elements to the external terminal on and off.

9. The circuit according to claim 7 , wherein the control circuit controls timings at which respective ones of said plurality of transistors are turned on and off by delaying operation of respective ones of the transistors.

10. A buffer circuit equipped with terminating resistors, comprising:

the termination circuit set forth in claim 7 ; and

an input circuit, output circuit or input/output circuit connected to said external connection terminal,

wherein said control circuit outputs an enable signal to said input circuit, output circuit or input/output circuit after on/off control in each of said plurality of resistance elements is completed.

11. A semiconductor integrated circuit device having the termination circuit set forth in claim 7 .