Nonvolatile semiconductor memory with erase gate and its manufacturing method

1. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a select gate formed above the semiconductor substrate;

a floating gate formed above the semiconductor substrate; and

an erase gate being adjacent to an edge of a lower surface of the floating gate, an upper surface of the erase gate being positioned lower than an upper surface of the floating gate.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein the floating gate is formed at a position corresponding to a lateral side of the select gate.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein at least a portion of the erase gate is formed lower than an upper surface of the semiconductor substrate.

4. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a device isolation structure formed on the semiconductor substrate,

wherein at least a portion of the erase gate is embedded within the device isolation structure.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein the erase gate includes a cavity located adjacent to the edge of the lower surface of the floating gate.

6. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a device isolation structure formed to protrude from a surface of the semiconductor substrate;

a trench formed within the device isolation structure; and

a tunnel insulation film formed on an inner wall of the trench,

wherein the erase gate is formed above the tunnel insulation film so as to be embedded within the trench.

7. The nonvolatile semiconductor memory device according to claim 6 , wherein the floating gate includes:

a lower section enclosed between an adjoining device isolation structure; and

an upper section formed on the lower section, and overlapping a portion of the device isolation structure, and

wherein the erase gate is located adjacent to an edge of a lower surface of the upper section via the tunnel insulation film.

8. The nonvolatile semiconductor memory device according to claim 7 , wherein the erase gate comprises a cavity located adjacent to the edge of the lower surface of the upper section.

9. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a program gate formed, via an insulation layer, above the floating gate.

10. The nonvolatile semiconductor memory device according to claim 9 , further comprising:

a silicide film formed above an upper surface of the program gate.

11. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a gate insulation film formed above a channel region of a surface of the semiconductor substrate;

a first diffusion region and a second diffusion region formed on the semiconductor substrate so as to enclose the channel region;

a plug coupled to the first diffusion region;

a first silicide film formed above an upper surface of the plug; and

a second silicide film formed above a surface of the second diffusion region.

12. The nonvolatile semiconductor memory device according to claim 1 , wherein electrons within the floating gate are extracted to the erase gate by a Fowler-Nordheim (FN) tunneling method.

13. The nonvolatile semiconductor memory device according to claim 1 , wherein the upper surface of the erase gate is positioned higher than the lower surface of the floating gate.

14. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a silicide film formed above the upper surface of the floating gate.

15. The nonvolatile semiconductor memory device according to claim 1 , further comprising:

a silicide film disposed on an upper surface of the select gate.

16. The nonvolatile semiconductor memory device according to claim 1 , wherein a lower surface of the erase gate is positioned lower than the lower surface of the floating gate.

17. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a select gate formed above the semiconductor substrate;

a floating gate formed above the semiconductor substrate on a side of the select gate;

a device isolation structure formed on the semiconductor substrate; and

an erase gate formed on the device isolation structure,

wherein the erase gate is positioned lower than an upper surface of the floating gate, and adjacent to an edge of a lower surface of the floating gate.

18. The nonvolatile semiconductor memory device according to claim 17 , further comprising:

a program gate formed above the floating gate;

a first diffusion region formed on the semiconductor substrate at a position adjacent to the floating gate;

a second diffusion region formed on the semiconductor substrate at a position adjacent to the select gate;

a plug formed above the first diffusion region, and coupled to the first diffusion region;

a first silicide film formed on an upper surface of the program gate;

a second silicide film formed on a surface of the plug;

a third silicide film formed on a surface of the select gate; and

a fourth silicide film formed on a surface of the second diffusion region.

19. The nonvolatile semiconductor memory device according to claim 17 , wherein an upper surface of the erase gate is positioned lower than the upper surface of the floating gate.

20. The nonvolatile semiconductor memory device according to claim 19 , wherein the upper surface of the erase gate is positioned higher than the lower surface of the floating gate.

21. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; and a memory cell array with a plurality of memory cells formed on the semiconductor substrate, wherein each of the plurality of memory cells includes: a select gate formed above the semiconductor substrate; a floating gate formed above the semiconductor substrate; and an erase gate being adjacent to an edge of a lower surface of the floating gate, an upper surface of the erase gate being positioned lower than an upper surface of the floating gate, and wherein the erase gate is jointly formed with a specified number of memory cells arrayed along a predetermined direction among the plurality of memory cells.

22. The nonvolatile semiconductor memory device according to claim 21 , wherein, in each of the plurality of memory cells, the floating gate is formed at a position corresponding to a lateral side of the select gate.