Data error recovery in non-volatile memory
View Patent ↗When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.
1. A method, comprising:
determining that binary data read from a specified range of sequential memory locations in a charge-based non-volatile (NV) memory contains errors that were uncorrected by an error correcting code (ECC) unit associated with the NV memory;
identifying which memory cells in the specified range produced data that is likely to be in error, said identifying to include
incrementing a read reference voltage through a range of voltage values,
reading, for each increment, binary data from within the specified range of sequential memory locations,
identifying which memory cells produce different binary data in a current increment than for a previous increment to determine analog charge values for the memory cells that produced different binary data, and
restoring the incremented read reference voltage and comparing the restored incremented read reference voltage to the analog charge values for the memory cells that produced different binary data to identify which memory cells in the specified range produced data that is likely to be in error;
changing the data for at least some of the memory cells whose data was determined to likely be in error; and
verifying whether the changed data is sufficiently correct for the ECC unit to provide correct data for the specified range.
2. The method of claim 1 , wherein said identifying further comprises:
producing a map of charge level values for the memory cells in at least the specified range; and
comparing the charge level values in groups of memory cells in the map to predefined patterns of charge levels, to identify which of the memory cells produced binary data likely to be in error.
3. The method of claim 1 , wherein said identifying further comprises:
determining analog charge values for memory cells in the specified range; and
determining which memory cells in the specified range have an analog charge value within a predetermined voltage amount of a read reference voltage for the NV memory.
4. The method of claim 1 , wherein said changing comprises adjusting analog charge values for the memory cells identified as likely to be in error.
5. The method of claim 1 , wherein said changing comprises substituting random binary data for the data from the memory cells identified as likely to be in error.
6. The method of claim 1 , wherein the specified range of sequential memory locations is a page of memory.
7. An apparatus, comprising
a computer system containing a processor and a charge-based non-volatile (NV) memory, the computer system to perform:
determining that binary data read from a specified range of sequential memory locations in the NV memory contains errors that were uncorrected by an error correcting code (ECC) unit associated with the NV memory;
identifying which memory cells in the specified range produced data that is likely to be in error, said identifying to include
incrementing a read reference voltage through a range of voltage values,
reading, for each increment, binary data from within the specified range of sequential memory locations,
identifying which memory cells produce different binary data in a current increment than for a previous increment to determine analog charge values for the memory cells that produced different binary data, and
restoring the incremented read reference voltage and comparing the restored incremented read reference voltage to the analog charge values for the memory cells that produced different binary data to identify which memory cells in the specified range produced data that is likely to be in error;
changing the data for at least some of the memory cells whose data was determined to likely be in error; and
verifying whether the changed data is sufficiently correct for the ECC unit to provide correct data for the specified range.
8. The apparatus of claim 7 , wherein said identifying further comprises:
producing a map of charge level values for the memory cells in at least the specified range; and
comparing the charge level values in groups of memory cells in the map to predefined patterns of charge levels, to identify which of the memory cells produced binary data likely to be in error.
9. The apparatus of claim 7 , wherein said identifying further comprises:
determining analog charge values for memory cells in the specified range; and
determining which memory cells in the specified range have an analog charge value within a predetermined voltage amount of a read reference voltage for the NV memory.
10. The apparatus of claim 7 , wherein said changing comprises adjusting analog charge values for the memory cells identified as likely to be in error.
11. The apparatus of claim 7 , wherein said changing comprises substituting random binary data for the data from the memory cells identified as likely to be in error.
12. An article comprising
a tangible computer-readable medium that contains instructions, which when executed by one or more processors result in performing operations comprising:
determining that binary data read from a specified range of sequential memory locations in a charge-based non-volatile (NV) memory contains errors that were uncorrected by an error correcting code (ECC) unit associated with the NV memory;
identifying which memory cells in the specified range produced data that is likely to be in error, said identifying to include
incrementing a read reference voltage through a range of voltage values,
reading, for each increment, binary data from within the specified range of sequential memory locations,
identifying which memory cells produce different binary data in a current increment than for a previous increment to determine analog charge values for the memory cells that produced different binary data, and
restoring the incremented read reference voltage and comparing the restored incremented read reference voltage to the analog charge values for the memory cells that produced different binary data to identify which memory cells in the specified range produced data that is likely to be in error;
changing the data for at least some of the memory cells whose data was determined to likely be in error; and
verifying whether the changed data is sufficiently correct for the ECC unit to provide correct data for the specified range.
13. The article of claim 12 , wherein the operation of identifying further comprises:
producing a map of charge level values for the memory cells in at least the specified range; and
comparing the charge level values in groups of memory cells in the map to predefined patterns of charge levels, to identify which of the memory cells produced binary data likely to be in error.
14. The article of claim 12 , wherein the operation of identifying further comprises:
determining analog charge values for memory cells in the specified range; and
determining which memory cells in the specified range have an analog charge value within a predetermined voltage amount of a read reference voltage for the NV memory.
15. The article of claim 12 , wherein the operation of changing comprises adjusting analog charge values for the memory cells identified as likely to be in error.
16. The article of claim 12 , wherein the operation of changing comprises substituting random binary data for the data from the memory cells identified as likely to be in error.
17. The article of claim 12 , wherein the specified range of sequential memory locations is a page of memory.