IP Library › Granted Patent US 7,884,470
Granted Patent B2
US 7,884,470 · App. 12/317,434 · Granted Feb 8, 2011

Semiconductor packages with stiffening support for power delivery

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,884,470
App. No.
12/317,434
Granted
Feb 8, 2011
Kind
B2
Abstract

Embodiments of the invention relate to semiconductor packages in which electrical power is delivered to die-side components removably installed in sockets formed between a package stiffener and an electrical conductor. To this purpose, the package stiffener and the electrical conductor may be electrically coupled to the power and ground terminals of the semiconductor package.

Claims (22)

1. A semiconductor package comprising:

a coreless substrate having a die-mounting zone;

a die disposed in the die-mounting zone;

a first electrical conductor mounted along a perimeter of the coreless substrate to provide stiffening support to the coreless substrate; and

a second electrical conductor mounted on the coreless substrate and spaced apart from the first electrical conductor to form a socket between the first electrical conductor and the second electrical conductor,

wherein the first and the second electrical conductor are coupled to a power terminal and a ground terminal to supply electrical power to at least a die-side component installed in the socket; and

an underfill material disposed in contact with the second electrical conductor, and wherein the die-side component is substantially free of solder at an interface between the die-side component and the coreless substrate.

2. The semiconductor package of claim 1 , wherein the die-side component is one of a capacitor, an inductor, a resistor, and a voltage regulator.

3. The semiconductor package of claim 1 , wherein the die-side component includes at least three of a capacitor, an inductor, a resistor, and a voltage regulator.

4. The semiconductor package of claim 1 , wherein the die-side component is substantially free of a solder at an interface between the die-side component and the substrate.

5. The semiconductor package of claim 1 , wherein the second electrical conductor is interposed between the first electrical conductor and the die-mounting zone.

6. The semiconductor package of claim 1 , wherein the first and the second electrical conductor are electrically coupled to the substrate by a solder.

7. A semiconductor package comprising:

a coreless substrate having a die-mounting zone;

a die disposed in the die-mounting zone;

a first electrical conductor mounted along a perimeter of the coreless substrate to provide stiffening support to the coreless substrate; and

a second electrical conductor mounted on the coreless substrate and spaced apart from the first electrical conductor to form a socket between the first electrical conductor and the second electrical conductor,

wherein the first and the second electrical conductor are coupled to a power terminal and a ground terminal to supply electrical power to at least a die-side component installed in the socket; and

an underfill material disposed in contact with the second electrical conductor, wherein the second electrical conductor provides a barrier support to the underfill material, and wherein the die-side component is substantially free of solder at an interface between the die-side component and the coreless substrate.

8. The semiconductor package of claim 6 , wherein the first electrical conductor is coupled to a power terminal and the second electrical conductor is coupled to a ground terminal.

9. The semiconductor package of claim 6 , wherein the die-side component includes at least three of a capacitor, an inductor, a resistor, and a voltage regulator.

10. The semiconductor package of claim 6 , wherein the first electrical conductor is coupled to a ground terminal, and the second electrical conductor is provided as electrically-separate portions which are coupled to a plurality of power terminals, and wherein the die-side component includes at least three of a capacitor, an inductor, a resistor, and a voltage regulator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2009
From: CHEAH, KEE LEONG; LEE, EU SOON
To: INTEL CORPORATION
Reel/Frame 022414/0492 →
Continuity (1)
Related Publication 20100155927A1 · Jun 24, 2010