Non-volatile memory cell with injector
In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the source of holes into the charge-storage layer of the charge storage stack. The injector has a barrier potential for holes which is less than an insulating layer of the charge-storage stack which is oriented towards the source of holes. A multi-layer crested barrier injector may have layers of increasing potential barriers for holes from the source to the charge-storage layer. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.
1. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source, wherein said injector comprises a hole permissive layer.
2. The NVM cell according to claim 1 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge-storage stack.
3. The NVM cell of claim 1 , wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
4. The NVM cell of claim 1 , wherein said charge storage layer is composed of charge trapping type material.
5. The NVM cell of claim 4 , wherein said charge trapping type material is silicon nitride.
6. The NVM cell of claim 5 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS, SANOS, MANOS and TANOS.
7. The NVM cell of claim 1 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
8. The NVM cell of claim 7 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
9. The NVM cell of claim 8 , wherein said injector is disposed between said stack and said gate.
10. The NVM cell of claim 8 , wherein said injector is disposed between said stack and said channel.
11. The NVM cell of claim 1 , wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
12. The NVM cell of claim 11 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
13. The NVM cell of claim 1 , wherein: said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises: a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
14. The NVM cell of claim 13 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).
15. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source, wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
16. The NVM cell according to claim 15 , wherein said injector comprises a hole permissive layer.
17. The NVM cell according to claim 16 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge-storage stack.
18. The NVM cell of claim 15 , wherein said charge storage layer is composed of charge trapping type material.
19. The NVM cell of claim 18 , wherein said charge trapping type material is silicon nitride.
20. The NVM cell of claim 19 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS, SANOS, MANOS and TANOS.
21. The NVM cell of claim 15 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
22. The NVM cell of claim 21 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
23. The NVM cell of claim 22 , wherein said injector is disposed between said stack and said gate.
24. The NVM cell of claim 22 , wherein said injector is disposed between said stack and said channel.
25. The NVM cell of claim 15 , wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
26. The NVM cell of claim 25 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
27. The NVM cell of claim 15 , wherein: said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises: a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
28. The NVM cell of claim 27 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).
29. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source, wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
30. The NVM cell according to claim 29 , wherein said injector comprises a hole permissive layer.
31. The NVM cell according to claim 30 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge-storage stack.
32. The NVM cell according to claim 29 , wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
33. The NVM cell of claim 29 , wherein said charge storage layer is composed of charge trapping type material.
34. The NVM cell of claim 33 , wherein said charge trapping type material is silicon nitride.
35. The NVM cell of claim 34 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS, SANOS, MANOS and TANOS.
36. The NVM cell of claim 29 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
37. The NVM cell of claim 36 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
38. The NVM cell of claim 37 , wherein said injector is disposed between said stack and said gate.
39. The NVM cell of claim 37 , wherein said injector is disposed between said stack and said channel.
40. The NVM cell of claim 29 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
41. The NVM cell of claim 29 , wherein: said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises: a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
42. The NVM cell of claim 41 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).
43. A nonvolatile memory (NVM) cell comprising:
a charge-storage stack comprising a charge-storage layer; a channel and a gate, between which said stack is disposed, wherein said channel or said gate is a hole source; and
an injector disposed between said charge-storage stack and said hole source, wherein said injector comprises at least one layer of a hole permissive material having a potential barrier for holes which is lower than that of an interface of the charge-storage stack; and said at least one layer of hole permissive material comprises:
a first layer of material disposed next to said hole source and having a first potential barrier for holes which is lower than that of an insulating layer of said charge-storage stack; and
a second layer of material disposed between the first layer of material and said insulating layer of the charge-storage stack and having a second potential barrier for holes which is lower than that of said insulating layer of the charge-storage stack and higher than that of said first layer of material.
44. The NVM cell according to claim 43 , wherein said injector comprises a hole permissive layer.
45. The NVM cell according to claim 44 , wherein said hole permissive layer is composed of a material having a potential barrier for holes which is lower than that of an interface of said charge-storage stack.
46. The NVM cell according to claim 43 , wherein said injector comprises a layer of material having a valence band energy which is higher than that of a top insulating layer of the charge-storage stack.
47. The NVM cell of claim 43 , wherein said charge storage layer is composed of charge trapping type material.
48. The NVM cell of claim 47 , wherein said charge trapping type material is silicon nitride.
49. The NVM cell of claim 48 , wherein said NVM cell is of a type selected from the group consisting of NROM, SONOS, SANOS, MANOS and TANOS.
50. The NVM cell of claim 43 , wherein said charge storage stack includes one or more insulating layers disposed between said charge storage layer and said gate or channel.
51. The NVM cell of claim 50 , wherein said insulating layer comprises oxide and said injector comprises a material selected from the group consisting of nitride (SiN), oxinitride (SiON), and silicon-rich nitride (SiRN).
52. The NVM cell of claim 51 , wherein said injector is disposed between said stack and said gate.
53. The NVM cell of claim 51 , wherein said injector is disposed between said stack and said channel.
54. The NVM cell of claim 43 , wherein said injector comprises a hole permissive layer comprised of gradated hole barrier material having increasing hole-barrier properties moving away from said hole source.
55. The NVM cell of claim 54 , wherein said gradated hole barrier material is comprised of at least two layers of dielectric materials arranged such that a potential barrier height peak for holes is near an interface between the injector and said charge-storage stack.
56. The NVM cell of claim 43 , wherein: said first layer of material is selected from the group consisting of nitride (SiN) and silicon-rich nitride (SiRN); and said second layer of material comprises oxinitride (SiON).