Semiconductor device, semiconductor wafer, and methods of producing the same device and wafer

1. A method of forming a multi-layered insulation film on a semiconductor wafer, comprising:

forming a methyl silsesquioxane (MSQ) layer by a spin-coating process;

forming a methylated hydrogen silsesquioxane (MHSQ) layer, such that the methylated hydrogen silsesquioxane (MHSQ) layer is in contact with a top of the methyl silsesquioxane (MSQ) layer; and

forming an inorganic insulation layer such that the inorganic insulation layer is in contact with a top of the methylated hydrogen silsesquioxane (MHSQ) layer.

2. The method according to claim 1 , wherein said forming said MSQ layer by said spin-coating process comprises:

dropping a solution comprising MSQ onto a rotating wafer;

thermally treating said solution in at least two stages such that said solution is dried and solidified into said MSQ layer.

3. The method according to claim 2 , wherein said thermally treating said solution comprises thermally treating said solution under a vacuum in a range from 1 Pa to 100 Pa for a period in a range from 1 minute to 10 minutes.

4. The method according to claim 1 , wherein said methylated hydrogen silsesquioxane (MHSQ) layer includes repeating units shown by formulae I, II and III

wherein a molar ratio of (II) to a total of I, II and III is at least 0.5.

5. The method according to claim 1 , further comprising:

forming, on a semiconductor substrate, a gate electrode with a side-wall insulation layer provided on a side, and a pair of impurity diffusion regions in a surface area of the semiconductor substrate on both sides of the gate electrode,

wherein forming said gate electrode comprises forming a plurality of gate electrodes having a side-wall insulation layer provided on a side, and a pair of impurity diffusion regions in a surface area of the semiconductor substrate on sides of the gate electrodes, said contact hole being formed between said plurality of gate electrodes,

wherein said forming said methyl silsesquioxane (MSQ) layer comprises forming said methyl silsesquioxane (MSQ) layer on said plurality of gate electrodes,

wherein said forming said methylated hydrogen silsesquioxane (MHSQ) layer comprises forming said methylated hydrogen silsesquioxane (MHSQ) layer on said plurality of gate electrodes, and

wherein said forming said inorganic insulation layer comprises forming said inorganic insulation layer on said plurality of gate electrodes.

6. The method according to claim 1 , wherein said forming said inorganic insulation layer comprises forming said inorganic insulation layer by plasma CVD.

7. The method according to claim 1 , wherein said methyl silsequioxane (MSQ) layer has a thickness which is greater than a thickness of said methylated hydrogen silsesquioxane (MHSQ) layer and greater than a thickness of said inorganic insulation layer.

8. The method according to claim 1 , further comprising:

forming a patterned photoresist on said inorganic insulation layer;

etching said MSQ layer, said MHSQ layer and said inorganic insulation layer by using said patterned photo resist, to form a contact hole in said MSQ layer, said MHSQ layer and said inorganic insulation layer;

removing said patterned photoresist by using an oxygen plasma;

forming a copper film in said contact hole; and

planarizing a surface of said copper film and a surface of said inorganic insulation layer by performing chemical mechanical polishing (CMP).

9. The method according to claim 8 , wherein said contact hole comprises a plurality of contact holes formed in said MSQ layer, said MHSQ layer and said inorganic insulation layer, and

wherein said copper film comprises a plurality of wires formed in said plurality of contact holes, such that said MSQ layer, MHSQ layer and inorganic insulation layer of said multilayered insulation film fill a space between said wires, a thickness of said plurality of wires in being in a range from 200 nm to 500 nm, and

wherein said planarizing said surface of said copper film and said surface of said inorganic insulation layer comprises planarizing a surface of said inorganic insulation layer and a surface of said plurality of wires, said MHSQ layer inhibiting a peeling away of said inorganic insulation layer during said planarization of said surface of said inorganic insulation layer and said plurality of wires.

10. A method of forming a multi-layered insulation film on a semiconductor wafer, comprising:

forming by a spin-coating process a first insulation layer comprising methyl silsesquioxane (MSQ);

forming a second insulation layer comprising a polysiloxane compound having an Si—H group where the second insulation layer contacts a top of the first insulation layer;

forming a third insulation layer comprising an inorganic material where the third insulation layer contacts a top of the second insulation layer; and

after said forming said third insulation layer, forming a plurality of grooves in said first, second and third insulation layers,

wherein said second insulation layer comprises a methylated hydrogen silsesquioxane (MHSQ) film.

11. The method according to claim 10 , wherein said methylated hydrogen silsesquioxane includes repeating units shown by formulae (I), (II) and (III):

wherein a molar ratio of (II) to a total of (I), (II) and (III) is at least 0.2.

12. The method according to claim 11 , wherein said molar ratio of II to a total of I, II and III is at least 0.5.

13. A method of producing a semiconductor device, comprising:

forming, on a semiconductor substrate, a gate electrode with a side-wall insulation layer provided on a side, and a pair of impurity diffusion regions in a surface area of the semiconductor substrate on both sides of the gate electrode;

forming a first insulation layer, which comprises methyl silsesquioxane (MSQ), over an entire surface of said substrate by using a spin-coating process;

forming a second insulation layer comprising a polysiloxane compound where the second insulation layer contacts a top of said first insulation layer;

forming a third insulation layer comprising an inorganic material where the third insulation layer contacts a top of said second insulation layer;

after said forming said third insulation layer, etching said first, second and third insulation layers to form a contact hole;

exposing said impurity diffusion regions to a bottom of said contact hole;

exposing said side-wall insulation layer to a side of said contact hole; and

forming an electroconductive film over the entire surface to fill said contact hole,

wherein said second insulation layer is highly adhesive,

wherein a dielectric constant of said first insulation layer is 3.0 or less, and

wherein said polysiloxane compound comprises methylated hydrogen silsesquioxane (MHSQ).

14. The method of producing a semiconductor device according to claim 13 , wherein said semiconductor substrate is spin-coated with a solution containing the MSQ and then thermally treated to form said first insulation layer, and said first insulation layer is thermally treated in atmosphere at 200° C. or more, and 500° C. or less, inclusive, coated with said second insulation layer by plasma CVD method.

15. The method according to claim 13 , wherein said third insulation layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride.

16. The method of producing a semiconductor device according to claim 13 , wherein forming said gate electrode comprises forming a plurality of gate electrodes having a side-wall insulation layer provided on a side, and a pair of impurity diffusion regions in a surface area of the semiconductor substrate on sides of the gate electrodes, said contact hole being formed between said plurality of gate electrodes,

wherein said forming said first insulation layer comprises forming said first insulation layer on said plurality of gate electrodes,

wherein said forming said second insulation layer comprises forming said second insulation layer on said plurality of gate electrodes, and

wherein said forming said third insulation layer comprises forming said third insulation layer on said plurality of gate electrodes.