Semiconductor integrated circuit device having standard cell including resistance element
View Patent ↗A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell.
1. A semiconductor integrated circuit device, comprising:
a first power supply wiring which receives a first voltage supply;
a second power supply wiring, which receives a second voltage supply and is laid in parallel to the first power supply wiring;
a plurality of standard cells provided in a substantially rectangular area having two sides that are a part of the first power supply wiring and a part of the second power supply wiring; and
at least one transistor resistance area provided in the rectangular area, wherein each of the standard cells includes:
a first well of a first conductivity provided along the first power supply wiring;
a second well of a second conductivity provided along the second power supply wiring and between the first well and the second power supply wiring;
a first-conductivity MOS transistor provided in the second well; and
a second-conductivity MOS transistor provided in the first well, wherein the transistor resistance area includes:
a third well of the first or second conductivity, having a substantially rectangular shape including two sides that are a portion of the first power supply wiring and a portion of the second power supply wiring; and
a plurality of MOS transistor resistances each having a conductivity opposite to that of the third well, and
wherein the plurality of MOS transistor resistances are arranged so that a number of MOS transistor resistances among the plurality of MOS transistor resistances are connected to each other serially, in parallel, or in a combination of serial and parallel connections between the first-conductivity MOS transistor and the second-conductivity MOS transistor.
2. The semiconductor integrated circuit device according to claim 1 , wherein a mask option for at least one of a contact and a wiring is used to connect the number of transistor resistances to each other.
3. The semiconductor integrated circuit device according to claim 1 , wherein in each of the standard cells, a source of the second-conductivity MOS transistor is connected to the first power supply wiring, a source of the first-conductivity MOS transistor is connected to the second power supply wiring, gates of the first-conductivity MOS transistor and the second-conductivity MOS transistor are connected in common to each other to form an input end, and a drain of the first-conductivity MOS transistor or the second-conductivity MOS transistor is used as an output end.
4. The semiconductor integrated circuit device according to claim 1 , wherein gates of the plurality of the first-conductivity MOS transistor resistances are connected to the first power supply wiring.
5. The semiconductor integrated circuit device according to claim 1 , wherein gates of the plurality of the second conductivity MOS transistor resistances are connected to the second power supply wiring.
6. The semiconductor integrated circuit device according to claim 1 , wherein the plurality of MOS transistors include several types of transistor resistances that are different from each other in transistor size.
7. The semiconductor integrated circuit device according to claim 4 , wherein the plurality of MOS transistors include several types of transistor resistances that are different from each other in transistor size.
8. The semiconductor integrated circuit device according to claim 5 , wherein the plurality of MOS transistors include several types of transistor resistances that are different from each other in transistor size.
9. The semiconductor integrated circuit device according to claim 1 , wherein each of the standard cells and each of the transistor resistance areas are disposed adjacently, and
wherein the first and third wells are common, or the second and third wells are common.
10. The semiconductor integrated circuit device according to claim 2 , wherein a wiring area related to the mask option includes a wiring laid at an integer multiple of a minimum interval of the wiring rule, so that a dummy wiring can be laid in a blank region between the wirings related to the mask option.