Signal processing method and circuit to convert analog signal to digital signal
View Patent ↗A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjacent two signal levels in each sampled digital signal by use of the sampling clocks, and monitors a polarity change in the differences, extracts a more inappropriate phase for use in sampling from phases of the sampling clocks on the basis of the absolute values of the differences where the polarity change is detected, and determines an antiphase of the extracted phase as a phase of the sampling clock to be provided to the analog-to-digital convertor.
1. A signal processing method, comprising:
sampling an analog signal to convert the analog signal to a digital signal as a signal conversion; and
executing a phase determination, including:
synchronizing the analog signal with sampling clocks having different phases, to obtain differences between each adjacent two signal levels in each sampled digital signal;
monitoring a polarity change in the differences;
extracting an inappropriate phase for use in sampling from the phases of the sampling clocks on a basis of absolute values of the differences where the polarity change is detected; and
determining an antiphase of the inappropriate phase extracted as a phase of a sampling clock, to execute the signal conversion.
2. The signal processing method according to claim 1 , wherein:
the phase determination includes extracting, as the inappropriate phase, among a respective maximum value of the absolute values of the differences where the polarity change is detected, a phase of a minimum value among the respective maximum value.
3. The signal processing method according to claim 1 , wherein:
the phase determination includes extracting, as the inappropriate phase, among a total sum of the absolute values of the differences where the polarity change is detected, a phase of a minimum value among the total sum.
4. The signal processing method according to claim 1 , wherein:
the phase determination includes extracting, as the inappropriate phase, among the absolute values of the differences where the polarity changes is detected, a phase of a minimum value among the absolute values.
5. A signal processing circuit, comprising:
a signal convertor which samples an analog signal, and converts the analog signal to a digital signal; and
a phase determination unit which obtains differences between each adjacent two signal levels in each sampled digital signal, by providing the signal convertor with sampling clocks with different phases, monitors a polarity change in the differences, extracts an inappropriate phase used for sampling among phases of the sampling clocks on a basis of absolute values of the differences where the polarity change has been detected, and determines an antiphase of the extracted phase as a phase of a sampling clock to be provided to the signal convertor.
6. The signal processing circuit according to claim 5 , wherein the phase determination unit extracts, as the inappropriate phase, among a respective maximum value of the absolute values of the differences where the polarity change is detected, a phase of a minimum value among the respective maximum value.
7. The signal processing circuit according to claim 5 , wherein the phase determination unit extracts, among a total sum of the absolute values of the differences where the polarity change is detected, a phase of a minimum value among the total sum.
8. The signal processing circuit according to claim 5 , wherein the phase determination unit extracts as the inappropriate phase, among the absolute values of the differences where the polarity changes is detected, a phase of a minimum value among the absolute values.
9. A signal processing circuit, comprising:
an analog-to-digital converter which converts an analog signal to a digital signal, based on a plurality of sampling clocks;
a clock generator which generates the plurality of sampling clocks, based on a synchronization signal, a frequency data and a phase data;
a frequency informing unit which outputs the frequency data, based on the synchronization signal;
a phase informing unit which outputs the phase data, based on a statistical information; and
an absolute difference statistics unit which outputs the statistical information, based on the plurality of sampling clocks and the digital signal, by monitoring a phase change of the digital signal.
10. The signal processing circuit as claimed in claim 9 , wherein the statistical information includes a data which corresponds to a minimum value among a plurality of differences between each adjacent two signal levels in each digital signal.
11. The signal processing circuit as claimed in claim 9 , wherein the absolute difference statistics unit comprises:
a difference detector which receives the digital signal, and outputs a difference between each adjacent two signal levels in each sampled digital signal;
an absolute value detector which is responsive to the difference to output an absolute difference;
a polarity change monitor which receives the difference to output a selection signal when a polarity of the difference is changed; and
a selector which selectively selects the absolute difference and a predetermined value, based on the selection signal.