Layout design method of semiconductor integrated circuit
View Patent ↗A layout design method of a semiconductor integrated circuit includes degenerating a layout netlist extracted from layout data, comparing the layout netlist after the reduction with a circuit diagram netlist, and creating a layout circuit association table of a layout cell after the reduction and a circuit element. The method includes creating a before and after reduction association table based on the layout netlist before and after the reduction, counting the number of layout elements in a layout cell area before the reduction, comparing the counted number of layout elements and the number of degenerated elements, and creating mapping information associating the layout cell with the circuit element.
1. A computer-implemented layout design method of a semiconductor integrated circuit, comprising:
degenerating, by a processor, a layout netlist extracted from a layout data, to produce a degenerated layout netlist;
comparing the degenerated layout netlist with a circuit diagram netlist, to produce a layout circuit association table of a degenerated layout cell and a circuit element;
creating a before and after reduction association table based on the layout netlist and the degenerated layout netlist;
counting a number of layout elements in a layout cell before the degenerating;
comparing the number of layout elements counted and a number of degenerated elements; and
creating a mapping information associating the layout cell with the circuit element.
2. The layout design method according to claim 1 , further comprising:
recording a coordinate of the layout element before the degenerating in reference to the layout circuit association table and the before and after reduction association table.
3. The layout design method according to claim 1 , wherein the mapping information is produced when the number of layout elements counted agrees with the number of the degenerated elements.
4. The layout design method according to claim 1 , wherein a plurality of layout elements are included in the layout cell.
5. The layout design method according to claim 1 , wherein the layout data comprises a mask pattern file in a binary.
6. A non-transitory computer-readable medium storing a computer program for causing a computer to perform a circuit layout design, comprising:
obtaining a degenerated element information from a layout information;
adding the degenerated element information and a layout before degenerating of the degenerated element information, into a circuit element list;
extracting a layout cell from a layout cell list; and
extracting a circuit element before degenerating in the layout cell extracted, from the circuit element list; and
counting the circuit element before degenerating in the layout cell extracted.