Semiconductor apparatus and anomaly detection method of the same

1. A semiconductor apparatus comprising:

an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node;

an internal oscillator that generates an internal clock signal to be used internally;

a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit, and output a notification signal; and

a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

2. The semiconductor apparatus according to claim 1 , wherein

the notification signal includes a first notification signal to be output when the count value reaches an advance notification maximum value being smaller than a predetermined upper limit of the execution time of the program in the arithmetic circuit, and a second notification signal to be output when the count value reaches the upper limit, and

the clock monitor circuit starts monitoring presence or absence of the operating clock signal in response to the first notification signal.

3. The semiconductor apparatus according to claim 2 , wherein

if the clock monitor circuit detects the operating clock signal,

after receiving the first notification signal, the arithmetic circuit outputs a WDT clear signal to reset a count value of the watch dog timer when no anomaly is recognized in the program being executed, and

after receiving the second notification signal, the arithmetic circuit forcibly terminates the program being executed in response to the second notification signal.

4. The semiconductor apparatus according to claim 1 , wherein

if the clock monitor circuit detects absence of the operating clock signal, the clock monitor circuit outputs a backup request signal to direct the arithmetic circuit to perform processing for restarting processing related to the program being executed in the arithmetic circuit.

5. The semiconductor apparatus according to claim 1 , further comprising:

a selector to switch a clock signal to be output to the clock transfer node when the clock monitor circuit does not detect the operating clock signal.

6. The semiconductor apparatus according to claim 5 , wherein

a plurality of external clock signals generated outside the semiconductor apparatus are input to the selector, and the selector outputs one of the plurality of external clock signals to the clock transfer node.

7. The semiconductor apparatus according to claim 6 , wherein

an external clock signal generated outside the semiconductor apparatus and the internal clock signal are input to the selector, and the selector outputs one of the external clock signal and the internal clock signal to the clock transfer node.

8. The semiconductor apparatus according to claim 2 , wherein

if the clock monitor circuit detects the operating clock signal and the arithmetic circuit outputs a WDT clear signal to reset a count value of the watch dog timer in response to the first notification signal,

the watch dog timer resets the count value to an initial value and continues counting,

the clock monitor circuit stops operating until the first notification signal is input next, and

the arithmetic circuit continues processing of the program being executed.

9. The semiconductor apparatus according to claim 2 , wherein

if the clock monitor circuit detects the operating clock signal and the arithmetic circuit does not output a WDT clear signal to reset a count value of the watch dog timer in response to the first notification signal,

the watch dog timer outputs the second notification signal, and

the arithmetic circuit forcibly terminates the program being executed in response to the second notification signal.

10. The semiconductor apparatus according to claim 2 , wherein

if the clock monitor circuit detects stop of the operating clock signal,

the clock monitor circuit switches a supply source of the operating clock signal and outputs a backup request signal to direct the arithmetic circuit to perform processing for restarting processing related to the program.

11. The semiconductor apparatus according to claim 10 , wherein

the arithmetic circuit outputs a WDT clear signal to reset a count value of the watch dog timer and performs processing for restarting processing related to the program based on the backup request signal after restart of supply of the operating clock signal.

12. The semiconductor apparatus according to claim 10 , wherein

if the watch dog timer does not receive a WDT clear signal to reset a count value of the watch dog timer from the arithmetic circuit even after restart of supply of the operating clock signal,

the watch dog timer outputs the second notification signal to the arithmetic circuit, and

the arithmetic circuit forcibly terminates the program being executed in response to the second notification signal.

13. An anomaly detection method in a semiconductor apparatus including an arithmetic circuit to execute a program based on an operating clock signal, the method comprising:

measuring an execution time of the program in the arithmetic circuit;

detecting presence or absence of the operating clock signal in response to the execution time reaching a preset value; and

determining which of an anomaly in the operating clock signal and an anomaly in the program causes an anomaly state in the arithmetic circuit.

14. The anomaly detection method according to claim 13 , wherein

if absence of the operating clock signal is detected and an anomaly state in the arithmetic circuit is caused by an anomaly in the operating clock signal, a supply source of the operating clock signal is switched.

15. The anomaly detection method according to claim 13 , wherein

if presence of the operating clock signal is detected and an anomaly state in the arithmetic circuit is caused by an anomaly in the program, the program being executed is forcibly terminated.

16. The anomaly detection method according to claim 14 , wherein

if presence of the operating clock signal is detected and an anomaly state in the arithmetic circuit is caused by an anomaly in the program, the program being executed is forcibly terminated.