Method for generating optimized constraint systems for retimable digital designs
A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.
1. A method for generating timing constraints for a digital circuit using a computer-driven system having at least a digital data storage and a digital data processor, comprising the steps of:
a step for describing said digital circuit using a hardware description language (HDL);
a step for constructing said digital circuit from said HDL description, using the computer-driven system; and
a step for constructing, using the computer-driven system, a system of clocks and artificial flip-flops by the following steps:
a step for assigning inputs to an input stage of the digital circuit;
a step for computing a length of a longest path from any input to each output;
a step for assigning outputs to stages as denoted by the longest path length;
a step for adding skips (1T delays) where alternative paths are shorter than the longest path;
a step for establishing a series of clocks (C 0 , C 1 , C 2 , . . . , wherein subscripts 0, 1, 2, etc, are integers that denote the sequence in the series of clocks) with a long clock period and a phase delay of T between successive members of said series;
for each output and input, a step for constructing a dummy flip-flop inserted in a path connecting said output and input; and
a step for clocking said dummy flip-flop with a clock whose subscript is a stage to which the input or output has been assigned;
whereby slack equivalence is created, in which timing slacks are equivalent to those in an optimized circuit.
2. A method for generating timing constraints for a digital circuit using a computer-driven system having at least a digital data storage and a digital data processor, comprising the operations of:
describing said digital circuit using a hardware description language (HDL);
constructing said digital circuit from said HDL description, using the computer-driven system; and
constructing, using the computer-driven system, a system of clocks and artificial flip-flops by the following operations:
assigning inputs to an input stage of the digital circuit;
computing a length of a longest path from any input to each output;
assigning said outputs to stages as denoted by the longest path length;
adding skips (1T delays) where alternative paths are shorter than the longest path;
establishing a series of clocks (C 0 , C 1 , C 2 , . . . , wherein subscripts 0, 1, 2, etc. are integers that denote the sequence in the series of clocks) with a long clock period and a phase delay of T between successive members of said series;
for each output and input, constructing a dummy flip-flop inserted in a path connecting said output and input; and
clocking said dummy flip-flop with a clock whose subscript is a stage to which the input or output has been assigned;
whereby slack equivalence is created, in which timing slacks are equivalent to those in an optimized circuit.
3. A non-transitory computer readable storage medium containing a first program or a second program or both first and second programs, the first program executable to perform operations to generate timing constraints, the second executable to install the first program on a computer, where the operations to generate timing constraints comprise:
describing a digital circuit using a hardware description language (HDL);
constructing said digital circuit from said HDL description; and
constructing a system of clocks and artificial flip-flops by the following operations:
assigning inputs to an input stage of the digital circuit;
computing a length of a longest path from any input to each output;
assigning said outputs to stages as denoted by the longest path length;
adding skips (1T delays) where alternative paths are shorter than the longest path;
establishing a series of clocks (C 0 , C 1 , C 2 , . . . , wherein subscripts 0, 1, 2, etc, are integers that denote the sequence in the series of clocks) with a long clock period and a phase delay of T between successive members of said series;
for each output and input, constructing a dummy flip-flop inserted in a path connecting said output and input; and
clocking said dummy flip-flop with a clock whose subscript is a stage to which the input or output has been assigned;
whereby slack equivalence is created, in which timing slacks are equivalent to those in an optimized circuit.
4. A computer driven system for generating timing constraints for a digital circuit, comprising:
digital data storage;
coupled to the digital data storage, a digital data processor programmed to perform operations comprising:
describing said digital circuit using a hardware description language (HDL);
constructing said digital circuit from said HDL description; and
constructing a system of clocks and artificial flip-flops by the following operations:
assigning inputs to an input stage of the digital circuit;
computing a length of a longest path from any input to each output;
assigning said outputs to stages as denoted by the longest path length;
adding skips (1T delays) where alternative paths are shorter than the longest path;
establishing a series of clocks (C 0 , C 1 , C 2 , . . . , wherein subscripts 0, 1, 2, etc, are integers that denote the sequence in the series of clocks) with a long clock period and a phase delay of T between successive members of said series;
for each output and input, constructing a dummy flip-flop; and
clocking said dummy flip-flop with a clock whose subscript is a stage to which the input or output has been assigned whereby slack equivalence is created, in which timing slacks are equivalent to those in an optimized circuit.