Semiconductor device and method of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate.
1. A semiconductor device comprising:
a trench having a predetermined depth in a semiconductor substrate, in a cell area of a semiconductor substrate and an interface area of the semiconductor substrate around the cell area
a device isolation layer pattern in the trench;
a floating gate pattern in the cell area of the semiconductor substrate;
a dummy floating gate pattern that extends from the floating gate pattern into the interface area around the cell area; and
a control gate pattern intersecting the floating gate pattern in the cell area of the semiconductor substrate.
2. The semiconductor device according to claim 1 , wherein the dummy floating gate pattern extends from a boundary of the cell area by 0.13 μm to 1.56 μm.
3. The semiconductor device according to claim 1 , wherein the dummy floating gate pattern is on the device isolation layer pattern.
4. The semiconductor device according to claim 1 , further comprising a dielectric layer on the floating gate pattern and the dummy floating gate pattern.
5. The semiconductor device according to claim 1 , wherein the floating gate pattern and the dummy floating gate pattern are part of a same layer.
6. The semiconductor device according to claim 1 , wherein the dummy floating gate pattern has a same length as the control gate pattern.
7. A method of fabricating a semiconductor device, the method comprising:
forming a trench having a predetermined depth in a cell area of a semiconductor substrate and an interface area of the semiconductor substrate around the cell area;
forming a device isolation layer in the trench;
forming a floating gate pattern in the cell area of the semiconductor substrate;
forming a dummy floating gate pattern, the dummy floating gate pattern extending from the floating gate pattern to an interface area around the cell area; and
forming a control gate pattern in the cell area of the semiconductor substrate, the control gate pattern intersecting the floating gate pattern.
8. The method according to claim 7 , wherein the forming of the control gate pattern comprises:
sequentially forming a polysilicon layer, an anti-reflection layer, and a photoresist layer over the semiconductor substrate having the floating gate pattern and the dummy floating gate pattern; and
selectively exposing and then developing the photoresist layer to form a photoresist pattern and patterning the anti-reflection layer and the polysilicon layer using the photoresist pattern as a mask.
9. The method according to claim 8 , wherein forming the anti-reflection layer comprises a spin-coating method.
10. The method according to claim 7 , wherein forming the dummy floating gate pattern and the floating gate pattern comprises depositing and patterning a same layer, and the dummy floating gate pattern comprises a portion of the patterned single layer that extends from a boundary of the cell area into the interface area by about 0.13 μm to 1.56 μm.
11. The method according to claim 7 , further comprising forming a dielectric layer on the dummy floating gate pattern and the floating gate pattern.
12. The method according to claim 7 , wherein a width of the dummy floating gate pattern ranges from about 0.13 μm to about 1.56 μm.
13. A semiconductor device comprising:
a trench having a predetermined depth in a cell area of a semiconductor substrate and in an interface area of the semiconductor substrate around the cell area;
a device isolation layer pattern in the trench;
floating gate patterns elongated in a first direction in the cell area of the semiconductor substrate;
a control gate pattern intersecting the floating gate patterns in the cell area of the semiconductor substrate in a second direction perpendicular to the first direction; and
a dummy floating gate pattern on the interface area in the second direction and spaced apart from one end of the floating gate pattern.
14. The semiconductor device according to claim 13 , wherein the dummy floating gate pattern has a same length as the control gate pattern.
15. The semiconductor device according to claim 13 , wherein a spaced distance between the floating gate pattern and the dummy floating gate pattern ranges from about 0.13 μm to about 1.56 μm.
16. The semiconductor device according to claim 13 , wherein a line width of the dummy floating gate pattern ranges from about 0.13 μm to about 1.56 μm.
17. A method of manufacturing a semiconductor device, the method comprising:
forming a trench having a predetermined depth in a cell area of a semiconductor substrate and an interface area of the semiconductor substrate around the cell area;
forming a device isolation layer in the trench;
forming floating gate patterns in the cell area of the semiconductor substrate;
forming dummy floating gate patterns in the interface area, the dummy floating gate patterns being spaced apart in a direction perpendicular to a length direction of the floating gate patterns; and
forming a control gate pattern in the cell area of the semiconductor substrate, the control gate pattern intersecting the floating gate pattern.
18. The method according to claim 17 , wherein the forming of the control gate pattern comprises:
sequentially forming a polysilicon layer, an anti-reflection layer, and a photoresist layer on an entire surface of the semiconductor substrate having the floating gate pattern and the dummy floating gate pattern; and
selectively exposing and then developing the photoresist layer to form a photoresist pattern and patterning the anti-reflection layer and the polysilicon layer using the photoresist pattern as a mask.
19. The method according to claim 18 , wherein forming the anti-reflection layer comprises a spin-coating method.
20. The method according to claim 17 , wherein forming the dummy floating gate patterns and the floating gate patterns comprises depositing and patterning a same layer, and the dummy floating gate patterns comprise a portion of the patterned single layer that extends from a boundary of the cell area into the interface area by about 0.13 μm to 1.56 μm.