MEMORY CONTROLLER AND A METHOD OF OPERATING AN ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY DEVICE

1 . A method of operating a non-volatile memory device having an array of non-volatile memory cells, susceptible to suffering loss of data stored in one or more memory cells of said array, and a controller for controlling the array of non-volatile memory cells, said memory device for interfacing with a host device and far receiving from the host device a time-stamp signal, said method comprising:

receiving by the controller the time stamp signal from the host device;

comparing the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and

determining when to perform a data retention and refresh operation for data stored in (he memory array based upon the comparing step.

2 . The method of claim 1 wherein the time stamp signal is sent by the host device upon power up of the memory device.

3 . The method of claim 1 wherein the time stamp signal is sent by the host device after a hardware reset of the host device.

4 . The method of claim 1 wherein the time stamp signal is sent by the host device after a software reset of the host device.

5 . The method of claim 1 further comprising the step of

performing the data retention and refresh operation in the event the result of the comparing step indicates the necessity of performing such operation.

6 . The method of claim 5 wherein the array of non-volatile memory cells has a plurality of blocks with each block having a plurality of memory cells mat are erased together, and wherein the controller having capability for detecting and correcting one or more errors in data stored in a block of memory cells.

7 . The method of claim 6 wherein the data retention and refresh operation comprises:

a) reading data from each of the memory cells from one of said blocks;

b) correcting said data read, if need be, to form corrected data, by the controller,

c) writing corrected data, if exists, to a different block of said array; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

8 . The method of claim 6 wherein the data retention and refresh operation comprises:

a) reading the data signal from each of the memory cells from one of said blocks;

b) comparing the data signal read to a margin signal;

c) writing the data corresponding to the data signal into a different memory cell of a different block of said array, in the event the result of the comparing step (b) indicates the necessity of writing the data corresponding to the data signal to a different memory cell; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

9 . A method of determining the integrity of data signals stored in an array of non-volatile memory cells, wherein the array of non-volatile memory cells is characterized by a plurality of blocks with each block having a plurality of non-volatile memory cells that are erased together, said method comprising:

a) reading data from each of the memory cells from one of said blocks;

b) correcting said data read, if need be, to form corrected data;

c) writing corrected data, if exists, to a different block of said array, and not writing the data read if the data read is uncorrected; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

10 . A method of determining the integrity of data signals stored in an array of non-volatile memory cells, wherein the array of non-volatile memory cells is characterized by a plurality of blocks with each block having a plurality of non-volatile memory cells that are erased together, said method comprising:

a) reading the data signal from each of the memory cells from one of said blocks;

b) comparing the data signal read to a margin signal;

c) writing the data corresponding to the data signal into a different memory cell of a different block of said array, in the event the result of the comparing step (b) indicates the necessity of writing the data corresponding to the data signal to a different memory cell, and not writing the data if otherwise; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

11 . A controller for operating a non-volatile memory device having an array of non-volatile memory cells, susceptible to suffering loss of data stored in one or more memory cells of said array, said controller for interfacing with a host device and for receiving, from the host device a time-stamp signal, said controller comprising:

a processor;

a memory having program code stored therein for execution by the processor, said program code configured to:

receiving by the controller the time stamp signal from the host device;

comparing the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and

determining when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.

12 . The controller of claim 11 wherein said an array of non-volatile memory cells has a plurality of blocks with each block having a plurality of memory cells that are erased together, wherein said program code is further configured to:

a) reading data from each of the memory cells from one of said blocks;

b) correcting said data read, if need be, to form corrected data, by the controller;

c) writing corrected data, if exists, to a different block of said array; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

13 . The controller of claim 11 wherein said an array of non-volatile memory cells has a plurality of blocks with each block having a plurality of memory cells that are erased together, wherein said program code is further configured to:

a) reading the data signal from each of the memory cells from one of said blocks;

b) comparing the data signal read to a margin signal;

c) writing the data corresponding to the data signal into a different memory cell of a different block of said array, in the event the result of the comparing step (b) indicates the necessity of writing the data corresponding to the data signal to a different memory cell; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

14 . A controller for operating a non-volatile memory device having an array of non-volatile memory cells, with said array of non-volatile memory cells having a plurality of blocks with each block having a plurality of memory cells that are erased together, said controller comprising:

a processor;

a memory having program code stored therein for execution by the processor, said program code configured to:

a) reading data from each of the memory cells from one of said blocks;

b) correcting said data read, if need be, to form corrected data;

c) writing corrected data, if exists, to a different block of said array, and not writing the data read if the data read is uncorrected; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

15 . A controller for operating a non-volatile memory device having an array of non-volatile memory cells, with said array of non-volatile memory cells having a plurality of blocks with each block having a plurality of memory cells that are erased together, said controller comprising:

a processor;

a memory having program code stored therein for execution by the processor, said program code configured to:

a) reading the data signal from each of the memory cells from one of said blocks;

b) comparing the data signal read to a margin signal;

c) writing the data corresponding to the data signal into a different memory cell of a different block of said array, in the event the result of the comparing step (b) indicates the necessity of writing the data corresponding to the data signal to a different memory cell, and not writing the data if otherwise; and

d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.