Memory interface device and methods thereof
View Patent ↗A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device, the load/store module determines a predicted coherency state of a cache line associated with the load or store instruction. Based on the predicted coherency state, the load/store module selects a bus transaction and communicates it to the bus. By selecting the bus transaction based on the predicted cache state, the load/store module does not have to wait for all pending bus transactions to be serviced, providing for greater predictability as to when bus transactions will be communicated to the bus, and allowing the bus behavior to be more easily simulated.
1. A method comprising:
receiving a first memory request associated with a first address;
in response to receiving the first memory request, determining, via a control module within a load/store module, a first predicted coherency state of a first cache location associated with the first address by selecting the first predicted coherency state from a plurality of possible states based on a type of a first pending bus transaction associated with the first address, the first pending bus transaction resulting from a second memory request received prior to the first memory request, the type of the first pending bus transaction selected from the group consisting of a load transaction and a store transaction;
determining, via the control module, a first bus transaction based on the first predicted coherency state; and
communicating the first bus transaction.
2. The method of claim 1 , wherein determining the first predicted coherency state comprises determining the first predicted coherency state based on a corresponding type of each of a plurality of pending bus transactions associated with the first address, the plurality comprising the first pending bus transaction, the type of each of the plurality of pending bus transactions selected from the group consisting of load transactions and store transactions.
3. The method of claim 1 , wherein the first predicted coherency state is selected from the group consisting of a shared state, a modified state, an exclusive state, or an invalid state.
4. The method of claim 1 , wherein the determining the first predicted coherency state comprises:
determining a link between the first pending bus transaction and a second pending bus transaction in response to determining the first pending bus transaction and the second pending bus transaction are associated with a common cache location; and
determining the first predicted coherency state based on the second pending bus transaction in response to determining the link.
5. The method of claim 1 , further comprising:
retiring the first pending bus transaction in response to receiving a retirement indication; and
transferring the first pending bus transaction from a pending bus transaction queue to a retired instruction queue in response to retiring the first pending bus transaction.
6. The method of claim 1 , further comprising:
receiving a third memory request associated with the first address;
determining a second predicted coherency state of the first cache location based on the first pending bus transaction;
determining a second bus transaction based on the second predicted coherency state; and
communicating the second bus transaction.
7. The method of claim 1 , further comprising:
receiving a second memory request associated with a second address;
determining a second predicted coherency state of a second cache location based on a second pending bus transaction associated with the second address;
determining a second bus transaction based on the second predicted coherency state; and
communicating the second bus transaction.
8. The method of claim 1 , wherein determining the first bus transaction comprises determining the first bus transaction based on a data size associated with the first memory request.
9. The method of claim 1 , wherein determining the first bus transaction comprises:
determining a set of available bus transaction types based on the first predicted coherency state; and
selecting the first bus transaction from the set of available bus transaction types.
10. The method of claim 1 , wherein the first predicted coherency state is not based on a type of the first memory request.
11. A method, comprising:
receiving a first stimulus indicative of a first simulated memory request associated with a first address;
determining, via a control module within a load/store module, a first predicted coherency state of a first simulated cache location associated with the first address based on a type of a first pending bus transaction associated with the first address, the first pending bus transaction resulting from a second simulated memory request received prior to the first stimulus, the type of the first pending bus transaction selected from the group consisting of a load transaction and a store transaction;
determining, via the control module, a first bus transaction based on the first predicted coherency state; and
simulating operation of a bus based on the first bus transaction.
12. The method of claim 11 , wherein simulating operation of the bus comprises determining a behavioral profile of a behavioral model based on the first bus transaction.
13. The method of claim 12 , further comprising creating an integrated circuit device design based on the behavioral profile.
14. The method of claim 13 , further comprising forming an integrated circuit based on the integrated circuit device design.
15. The method of claim 11 , wherein determining the first predicted coherency state comprises determining the first predicted coherency state based on a plurality of pending bus transactions associated with the first address, the plurality comprising the first pending bus transaction.
16. A device, comprising:
a cache;
a load/store module further comprising:
a pending bus transaction queue comprising an input configured to receive bus transactions and an output coupled to a bus, the pending bus transaction queue configured to store pending bus transactions associated with the cache; and
a control module comprising an input configured to receive a first memory request associated with the cache, an input coupled to the cache and an output coupled to the input of the pending bus transaction queue, the output configured to communicate bus transactions in response to the memory requests, the control module configured to select one or more of the bus transactions based on a predicted coherency state of a cache line of the cache, the predicted coherency state based on types of pending bus transactions stored at the pending bus transaction queue prior to receiving the first memory request, the types of pending bus transactions selected from the group consisting of load transactions and store transactions.
17. The device of claim 16 , wherein the control module is configured to determine the predicted coherency state based on the pending bus transactions.
18. The device of claim 16 , further comprising:
a bus configured to receive the bus transactions;
a coherency control module coupled to the bus, the coherency control module configured to determine a plurality of coherency messages based on the bus transactions; and
a memory coupled to the coherency control module, the memory configured to store or retrieve data in response to one or more of the bus transactions.
19. The device of claim 16 , further comprising:
a processor coupled to the input of the control module to provide the memory requests.
20. The device of claim 16 , wherein the predicted coherency state is selected from the group consisting of a shared state, a modified state, an exclusive state, or an invalid state.