AC impedance spectroscopy testing of electrical parametric structures
Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.
1. A method of electronic testing, comprising the steps of:
providing an electronic component in an integrated circuit;
applying a sinusoidal voltage signal to said electronic component at a non-zero frequency and measuring in-phase and out-of-phase current components of said component;
varying the frequency of the applied signal in discrete steps from less than 10 Hz to above 100 MHz while repeating the measurement of the in-phase and out-of-phase current components of said electronic component at each frequency;
varying the amplitude of the applied signal in discrete steps while repeating the above step of varying the frequency of the applied signal while repeating the measurement of the in-phase and out-of-phase current components of said electronic component at each frequency and amplitude;
computing an in-phase impedance for each said in-phase current component value;
computing an out-of-phase impedance for each said out-of-phase current component value; and
analyzing said in-phase impedance values and said out-of-phase impedance values using a Nyquist plot, in which said in-phase impedance values are plotted on an x-axis of an x-y chart and said out-of-phase impedance values are plotted on a y-axis of an x-y chart.
2. The method of claim 1 , in which:
said in-phase impedance is computed using the expression V amplitude /I in-phase — max in which V amplitude is an amplitude of said sinusoidal voltage signal and I in-phase — max is an amplitude of said in-phase current component; and
said out-of-phase impedance is computed using the expression V amplitude /I out-of-phase — max in which V amplitude is an amplitude of said sinusoidal voltage signal and I out-of-phase — max is an amplitude of said out-of-phase current component.
3. The method of claim 2 , wherein said component is a contact continuity chain test circuit.
4. The method of claim 2 , wherein said component is a via continuity chain test circuit.
5. The method of claim 2 , wherein said component is an MOS gate dielectric integrity test circuit.
6. The method of claim 2 , wherein said component is a metal line continuity test circuit.
7. The method of claim 2 , wherein said component is a metal isolation test circuit comprised of metal interconnect lines which are separated by a dielectric material.
8. The method of claim 2 , wherein said electronic component is tested during fabrication of said integrated circuit.
9. The method of claim 2 , wherein said integrated circuit is partially deprocessed.
10. A method of fabricating an integrated circuit, comprising the steps of:
providing a substrate;
forming field oxide in said substrate;
forming an n-well in said substrate;
forming a p-well in said substrate;
forming an n-channel MOS transistor in said p-well by a process comprising the steps of:
forming a first gate dielectric on a top surface of said p-well;
forming a first gate structure on a top surface of said first gate dielectric;
forming n-type source and drain regions in said p-well adjacent to said first gate structure; and
forming a first set of silicide regions on, and in contact with, top surfaces of said n-type source and drain regions;
forming a p-channel MOS transistor in said n-well by a process comprising the steps of:
forming a second gate dielectric on a top surface of said n-well;
forming a second gate structure on a top surface of said second gate dielectric;
forming p-type source and drain regions in said n-well adjacent to said second gate structure; and
forming a second set of silicide regions on, and in contact with, top surfaces of said p-type source and drain regions;
forming a pre-metal dielectric layer stack on said n-channel transistor and said p-channel transistor;
forming contacts in said pre-metal dielectric layer stack on, and electrically connected to, said n-well, said p-well, said n-type source and drain regions and said p-type source and drain regions;
forming a first intra-metal dielectric layer on said pre-metal dielectric layer stack;
forming a first set of metal interconnect structures in said first intra-metal dielectric layer;
forming a first inter-level dielectric layer on said first set of metal interconnect structures;
forming metal vias in said first inter-level dielectric layer, whereby the metal vias contact said first set of metal interconnect structures;
forming a second set of metal interconnect structures in said first inter-level dielectric layer, whereby the second set of metal interconnect structures contact and overlap said metal vias; and
testing a component in said integrated circuit, comprising the steps of;
applying a sinusoidal voltage signal to said component at a non-zero frequency and measuring in-phase and out-of-phase current components of said component;
varying the frequency of the applied signal in discrete steps from less than 10 Hz to above 100 MHz while repeating the measurement of the in-phase and out-of-phase current components of said electronic component at each frequency;
varying the amplitude of the applied signal in discrete steps while repeating the above step of varying the frequency of the applied signal while repeating the measurement of the in-phase and out-of-phase current components of said electronic component at each frequency and amplitude;
computing an in-phase impedance for each said in-phase current component value;
computing an out-of-phase impedance for each said out-of-phase current component value; and
analyzing said in-phase impedance values and said out-of-phase impedance values using a Nyquist plot, in which said in-phase impedance values are plotted on an x-axis of an x-y chart and said out-of-phase impedance values are plotted on a y-axis of an x-y chart.
11. The method of claim 10 , in which:
said in-phase impedance is computed using the expression V amplitude /I in-phase — max in which V amplitude is an amplitude of said sinusoidal voltage signal and I in-phase — max is an amplitude of said in-phase current component; and
said out-of-phase impedance is computed using the expression V amplitude /I out-of-phase — max in which V amplitude is an amplitude of said sinusoidal voltage signal and I out-of-phase — max is an amplitude of said out-of-phase current component.
12. The method of claim 11 , wherein said component is a contact continuity chain test circuit.
13. The method of claim 11 , wherein said component is a via continuity chain test circuit.
14. The method of claim 11 , wherein said component is an MOS gate dielectric integrity test circuit.
15. The method of claim 11 , wherein said component is a metal line continuity test circuit.
16. The method of claim 11 , wherein said component is a metal isolation test circuit comprised of metal interconnect lines which are separated by a dielectric material.
17. The method of claim 11 , wherein said electronic component is tested during fabrication of said integrated circuit.
18. The method of claim 11 , wherein said integrated circuit is partially deprocessed.