IP Library Granted Patent US 8,247,883
Granted Patent B2
US 8,247,883 · App. 12/328,694 · Granted Aug 21, 2012

Printing shielded connections and circuits

Assignee: Palo Alto Research Center Incorporated
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Quick Facts
Patent No.
US 8,247,883
App. No.
12/328,694
Granted
Aug 21, 2012
Kind
B2
Abstract

An embodiment is a method and apparatus to construct a shielded cable, wire, or circuit. A first insulator layer is deposited on a first conductor or semiconductor layer. A second conductor or semiconductor layer is deposited on the first insulator layer. A second insulator layer is deposited on the first insulator layer. The second insulator layer covers the second conductor or semiconductor layer and defines a shielded region. A third conductor or semiconductor layer is deposited on the first conductor or semiconductor layer. The third conductor or semiconductor layer covers the first and second insulator layers. At least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing.

Claims (57)

1. An apparatus comprising:

a first conductor or semiconductor layer;

a first insulator layer deposited on the first conductor or semiconductor layer;

a second conductor or semiconductor layer deposited on the first insulator layer;

a second insulator layer deposited on the first insulator layer and covering the second conductor or semiconductor layer, the second insulator layer defining a shielded region; and

a third conductor or semiconductor layer deposited on the first conductor or semiconductor layer and encapsulating the first and second insulator layers;

wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing, and

wherein one of the first and second conductor or semiconductor layers is a gate and the third conductor or semiconductor layer includes a source and drain of a transistor device.

2. The apparatus of claim 1 wherein the first conductor or semiconductor layer is a conductive substrate.

3. The apparatus of claim 1 wherein the first conductor or semiconductor layer is deposited on a substrate.

4. The apparatus of claim 1 wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layer is deposited by inkjet printing.

5. The apparatus of claim 1 wherein at least one of the first, second, and third conductor or semiconductor layers is made of a printed conductor.

6. The apparatus of claim 1 wherein at least one of the first and second insulator layers is made from one of printed polymer solutions, printed polymer particles, precursors for inorganic insulators, silicones, polysilsesquioxanes, inorganic particles, hybrid organic-inorganic insulators, and a piezoelectric polymer.

7. The apparatus of claim 6 wherein the printed conductor is made of one of polyacetylene, polyaniline, a polymer mixture of two ionomers, sintered metal nanoparticles, a metal precursor, carbon nanotubes, metal nanowires, and a printed seed material for plating.

8. The apparatus of claim 1 wherein the shielded region further comprises an active component.

9. The apparatus of claim 8 wherein the active component is an electrical component or an optical component.

10. The apparatus of claim 1 wherein at least one of the first and second insulator layers is a piezoelectric polymer.

11. The apparatus of claim 10 wherein at least one of the first and second insulation layers includes a curable polymer.

12. An apparatus comprising:

a first conductor or semiconductor layer;

a first insulator layer deposited on the first conductor or semiconductor layer;

a second conductor or semiconductor layer deposited on the first insulator layer;

a second insulator layer deposited on the first insulator layer and covering the second conductor or semiconductor layer, the second insulator layer defining a shielded region; and

a third conductor or semiconductor layer deposited on the first conductor or semiconductor layer and encapsulating the first and second insulator layers;

wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing

a fourth conductor or semiconductor layer deposited on the second insulator layer; and

a third insulator layer deposited on the second insulator layer and covering the fourth conductor or semiconductor layer, the third insulator layer being within the third conductor or semiconductor layer.

13. The apparatus of claim 1 further comprising:

a branch-connection to accommodate a shielded assembly.

14. A method comprising:

forming a first conductor or semiconductor layer;

depositing a first insulator layer on the first conductor or semiconductor layer;

depositing a second conductor or semiconductor layer on the first insulator layer;

depositing a second insulator layer on the first insulator layer, the second insulator layer covering the second conductor or semiconductor layer and defining a shielded region; and

depositing a third conductor or semiconductor layer on the first conductor or semiconductor layer, the third conductor or semiconductor layer encapsulating the first and second insulator layers;

wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing, and

wherein one of the first and second conductor or semiconductor layers is a gate and the third conductor or semiconductor layer includes a source and drain of a transistor device.

15. The method of claim 14 wherein the first conductor or semiconductor layer is a conductive substrate.

16. The method of claim 14 wherein the first conductor or semiconductor layer is deposited on a substrate.

17. The method of claim 14 wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is printed by inkjet printing.

18. The method of claim 14 wherein at least one of the first, second, and third conductor or semiconductor layers is made of a printed conductor.

19. The method of claim 18 wherein the printed conductor is made of one of polyacetylene, polyaniline, a polymer mixture of two ionomers, sintered metal nanoparticles, a metal precursor, carbon nanotubes, metal nanowires, and a printed and plated seed material.

20. The method of claim 14 wherein at least one of the first and second insulator layers is made from one of printed polymer solutions, printed polymer particles, precursors for inorganic insulators, silicones, polysilsesquioxanes, inorganic particles, hybrid organic-inorganic insulators, and a piezoelectric polymer.

21. The method of claim 14 further comprising forming an active component inside the shielded region.

22. A circuit comprising:

a sensor to generate a sensing signal;

an input circuit to read the sensing signal; and

a shielded cable connecting the sensor to the input circuit, the shielded cable comprising:

a first conductor or semiconductor layer,

a first insulator layer deposited on the first conductor or semiconductor layer,

a second conductor or semiconductor layer deposited on the first insulator layer,

a second insulator layer deposited on the first insulator layer and covering the second conductor or semiconductor layer, the second insulator layer defining a shielded region, and

a third conductor or semiconductor layer deposited on the first conductor or semiconductor layer and encapsulating the first and second insulator layers;

wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing, and

wherein one of the first and second conductor or semiconductor layers is a gate and the third conductor or semiconductor layer includes a source and drain of a transistor device.

23. The circuit of claim 22 wherein the first conductor or semiconductor layer is a conductive substrate.

24. The circuit of claim 22 wherein the first conductor or semiconductor layer is deposited on a substrate.

Assignments (9)
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
CONFIRMATORY LICENSE Recorded Apr 6, 2016
From: PALO ALTO RESEARCH CENTER, INCORPORATED
To: US ARMY, SECRETARY OF THE ARMY
Reel/Frame 038362/0421 →
CONFIRMATORY LICENSE Recorded Apr 21, 2010
From: PALO ALTO RESEARCH CENTER, INCORPORATED
To: US ARMY, SECRETARY OF THE ARMY
Reel/Frame 024262/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2008
From: DANIEL, JURGEN H.; NG, TSE NGA
To: PALO ALTO RESEARCH CENTER INCORPORATED
Reel/Frame 021927/0945 →
Continuity (1)
Related Publication 20100140673A1 · Jun 10, 2010