Semiconductor device and method of fabricating the same
Disclosed are a semiconductor device and method of fabricating the same. The semiconductor device includes a floating gate on a semiconductor layer; a first contact on the floating gate; a MIM capacitor including a lower electrode, an insulating layer, and an upper electrode on the first contact; a second contact on a drain region of the semiconductor layer; a metal island on the second contact; a via on the metal island; and a bit line on the via.
1. A semiconductor device comprising:
a floating gate on a semiconductor layer;
a first contact on the floating gate;
a MIM capacitor including a lower electrode, an insulating layer, and an upper electrode on the first contact;
a second contact on a drain region of the semiconductor layer;
a metal island on the second contact;
a via on the metal island; and
a bit line on the via.
2. The semiconductor device of claim 1 , wherein the MIM capacitor serves as a control gate function of a flash cell.
3. The semiconductor device of claim 1 , wherein the upper electrode serves as a function of a word line.
4. The semiconductor device of claim 1 , wherein the lower electrode comprises titanium (Ti), titanium nitride (TiN), or a titanium/titanium nitride (Ti/TiN) stack.
5. The semiconductor device of claim 1 , wherein the metal island and the upper electrode are formed on a same layer.
6. The semiconductor device of claim 1 , wherein the upper electrode comprises aluminum or aluminum alloy.
7. The semiconductor device of claim 1 , wherein the upper electrode comprises copper.
8. The semiconductor device of claim 1 , wherein the insulating layer comprises an oxide layer/nitride layer/oxide layer structure.
9. The semiconductor device of claim 1 , wherein the insulating layer comprises a nitride layer/oxide layer structure.
10. A method of fabricating a semiconductor device, the method comprising:
forming a floating gate on a semiconductor layer;
forming a first contact on the floating gate, and forming a second contact on a drain area of the semiconductor layer;
forming a MIM capacitor including a lower electrode, an insulating layer, and an upper electrode on the first contact, and forming a metal island on the second contact;
forming a via on the metal island; and
forming a bit line on the via.
11. The method of claim 10 , wherein the MIM capacitor serves as a control gate function of a flash cell.
12. The method of claim 10 , wherein the upper electrode serves as a function of a word line.
13. The method of claim 10 , wherein the lower electrode comprises titanium (Ti), titanium nitride (TiN), or a titanium/titanium nitride (Ti/TiN) stack.
14. The method of claim 10 , wherein the upper electrode comprises aluminum or aluminum alloy.
15. The method of claim 10 , wherein the upper electrode comprises copper.
16. The method of claim 10 , wherein the insulating layer comprises an oxide layer/nitride layer/oxide layer structure.
17. The method of claim 10 , wherein the insulating layer comprises a nitride layer/oxide layer structure.