Flash converter differential reference ladder auto-zero circuit
A differential reference ladder with an auto zero circuit that can be used as part of a flash analog to digital converter. The auto zero operation is performed relative to a common mode voltage of the ladder. The resistive ladder is disconnected from the rest of the circuit during auto zero mode. As a result, the auto zero adjustment is more accurate, since the offsets are stored under the same common mode connection as when the circuit is in a compare mode. This permits auto zeroing to proceed quickly unencumbered by the parasitic capacitance of the ladder or other components.
1. An apparatus comprising:
an array of comparators;
a resistive ladder, comprising a plurality of resistors, for establishing a common mode voltage and two or more reference voltages;
a plurality of buffers, for buffering the common mode voltage and reference voltages;
a plurality of switches, disposed between the resistive ladder and output buffers, to isolate the resistive ladder in an auto zero mode, by coupling the buffer inputs to the common mode voltage in the auto zero mode; and
at least one offset storage capacitor associated with each comparator for storing an auto zero offset voltage sampled in the auto zero mode.
2. The apparatus of claim 1 wherein the comparators are further arranged to have a first input coupled to receive an input signal sample and a second input coupled to receive a corresponding output of one of the buffers.
3. The apparatus of claim 2 wherein the outputs of the comparators provide a flash-type analog to digital converter having an output representative of the input signal sample.
4. The apparatus of claim 2 additionally wherein the switches are arranged so that, during a normal sample mode, the common mode voltage and reference voltages from the ladder are not isolated from and coupled to inputs of corresponding ones of the buffers.
5. The apparatus of claim 4 wherein the auto zero mode is enabled prior to taking each of a series of input signal samples.
6. The apparatus of claim 1 wherein each of the plurality of switches further comprises:
a series connected switch, disposed in series between one of the resistors and an input of a corresponding buffer; and
a common mode switch, connected between the common mode voltage and the inputs of the buffers.
7. The apparatus of claim 2 wherein the input signal sample is taken from a floating diffusion.
8. The apparatus of claim 2 wherein the input signal sample is provided as a differential floating diffusion, the reference ladder provides differential reference voltages, and each of the comparators provide a differential comparator output.
9. The apparatus of claim 3 wherein the analog to digital converter is part of a digital radio frequency receiver.
10. A flash analog to digital converter apparatus comprising:
a differential resistive ladder, for establishing a common mode voltage and two or more reference voltages;
a plurality of buffers, for buffering the common mode voltage and differential reference voltages;
a plurality of switches, disposed between the resistive ladder and output buffers, to isolate the resistive ladder in an auto zero mode, by coupling the buffer inputs to the common mode voltage;
an array of differential comparators, each connected to receive a differential input signal sample and a differential pair of the reference voltages; and
a pair of storage capacitors associated with each differential comparator, for storing a differential auto zero offset voltage sampled in the auto zero mode.
11. A method comprising:
establishing a common mode voltage and two or more reference voltages at respective output nodes of a resistive voltage ladder;
buffering the common mode voltage and reference voltages;
comparing the buffered reference voltages and common mode voltage to an input signal sample;
isolating the output nodes of the resistive ladder in an auto zero mode, by coupling the buffered reference voltages to the common mode voltage in the auto zero mode; and
sampling an auto zero offset voltage in the auto zero mode.
12. The method of claim 11 further comprising:
storing the sampled auto zero offset voltage in the auto zero mode.
13. The method of claim 12 wherein the comparing step provide a flash-type analog to digital conversion result representative of the input signal sample.
14. The method of claim 12 additionally comprising:
during a normal sample mode, coupling the reference voltages to corresponding buffer inputs so that the reference ladder is no longer isolated.
15. The method of claim 14 wherein the auto zero mode is enabled prior to taking each of a series of input signal samples.
16. The method of claim 11 comprising:
switching a series connection between a node of the ladder and an input of a corresponding buffer; and
switching a common mode connection between the common mode voltage and the inputs of the buffers.
17. The method of claim 12 wherein the input signal sample is taken from a floating diffusion.
18. The method of claim 12 wherein the input signal sample is provided as a differential floating diffusion, the reference ladder provides differential reference voltages, and each of the comparators provide a differential comparator output.
19. The method of claim 13 wherein the analog to digital converter is part of a digital radio frequency receiver.
20. A method of providing a flash analog to digital conversion result comprising:
establishing a common mode voltage and two or more reference voltages at a differential ladder;
buffering the common mode voltage and differential reference voltages at a plurality of buffers;
operating a plurality of switches, disposed between the resistive ladder and output buffers, to isolate the resistive ladder in an auto zero mode, by coupling the buffer inputs to the common mode voltage;
providing a plurality of differential comparison results, by comparing a differential input signal sample and a differential pair of the reference voltages; and
storing a differential auto zero offset voltage sampled in the auto zero mode on a pair of storage capacitors.