Substrate for wiring, semiconductor device for stacking using the same, and stacked semiconductor module
View Patent ↗In a stacked semiconductor module, a test covering connecting terminals is easily conducted and high reliability is achieved.
1. A semiconductor device, comprising:
a substrate having a side surface, a first surface and a second surface being opposed to the first surface;
a semiconductor chip; connecting terminals on the first surface of the substrate, the connecting terminals including first connecting terminals and second connecting terminals disposed outside the first connecting terminals in plan view;
external electrode terminals on the second surface of the substrate;
metal lines electrically connected to the second connecting terminals;
a solder resist disposed on the first surface of the substrate,
wherein the semiconductor chip is connected to the first surface of the substrate via the first connecting terminals, all of the first connecting terminals being disposed directly under the semiconductor chip,
the second connecting terminals are connected to another semiconductor device, and each of the metal lines is exposed from the side surface and the solder resist; and
wherein the metal lines include first metal lines and second metal lines, the first metal lines are disposed in same plane as the second connecting terminals, and the second metal lines are disposed under the connecting terminals.
2. A semiconductor device, comprising:
a substrate having a side surface, a first surface and a second surface being opposed to the first surface;
a semiconductor chip; connecting terminals on the first surface of the substrate, the connecting terminals including first connecting terminals and second connecting terminals disposed outside the first connecting terminals in plan view;
external electrode terminals on the second surface of the substrate; and
first and second metal lines electrically connected to the second connecting terminals,
wherein the semiconductor chip is connected to the first surface of the substrate via the first connecting terminals, all of the first connecting terminals being disposed directly under the semiconductor chip,
the second connecting terminals are connected to another semiconductor device,
the first metal lines are disposed on the first surface, and
the second metal lines are disposed in a layer of the substrate under the first surface; and
wherein each of the metal lines is exposed from the side surface of the substrate.
3. The semiconductor device according to claim 2 , further comprising a solder resist disposed on the first surface of the substrate.
4. A semiconductor device, comprising:
a substrate having a side surface, a first surface and a second surface being opposed to the first surface;
a semiconductor chip;
connecting terminals on the first surface of the substrate, the connecting terminals including first connecting terminals and second connecting terminals disposed outside the first connecting terminals in plan view;
external electrode terminals on the second surface of the substrate; and
metal lines electrically connected to the second connecting terminals,
wherein the semiconductor chip is connected to the first surface of the substrate via the first connecting terminals, all of the first connecting terminals being disposed directly under the semiconductor chip,
the second connecting terminals are connected to other semiconductor device, and
at least one of the metal lines extends from at least one of the second connecting terminals to the side surface of the substrate; and
a resin covering at least a portion of a side surface of the semiconductor chip, wherein all of the second connecting terminals are disposed outside a peripheral edge of the resin.
5. The semiconductor device according to claim 4 ,
wherein each of the metal lines is exposed from the side surface of the substrate.
6. The semiconductor device according to claim 4 ,
wherein each of end portions of the metal lines lies in a substantially same plane.
7. The semiconductor device according to claim 4 ,
wherein each of end portions of the metal lines forms a substantially straight line.
8. The semiconductor device according to claim 4 ,
wherein each of the metal lines are connected to a test terminal.
9. The semiconductor device according to claim 8 ,
wherein the test terminal is disposed outside a dicing line in the substrate, and
after dividing the substrate along the dicing line into the semiconductor device, the test terminal is not a portion of the substrate in the semiconductor device.
10. The semiconductor device according to claim 4 , further comprising a solder resist disposed on the first surface of the substrate.
11. The semiconductor device according to claim 4 , further comprising only two metal layers including a first metal layer and a second metal layer over the first metal layer disposed between the connecting terminals and the external electrode terminals in the substrate.
12. The semiconductor device according to claim 11 ,
wherein at least one of the first connecting terminals are connected to the first metal layer by a first via and at least one of the second connecting terminals are connected to the first metal layer by a second via, and
the first via and the second via are disposed in a same layer.
13. The semiconductor device according to claim 4 ,
wherein the metal lines are disposed between the connecting terminals and the external electrode terminals in the substrate.
14. The semiconductor device according to claim 4 ,
wherein the metal lines include first metal lines and second metal lines,
the first metal lines are disposed in same plane as the second connecting terminals, and
the second metal lines are disposed under the connecting terminals.
15. The semiconductor device according to claim 4 ,
wherein a width of each of the metal lines is smaller than half of a width of each of the second connecting terminals.
16. The semiconductor device according to claim 4 ,
wherein at least one of the second connecting terminals are connected to the other semiconductor device by at least one of members, and
a height of each of the members is larger than a height of each of the external electrode terminals.