Semiconductor structure and method of manufacture

1. A method to manufacture a semiconductor structure, comprising:

removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity that extends at least about one micron or greater below the surface of the semiconductor material, a second cavity that extends at least about one micron or greater below the surface of the semiconductor material, wherein the first cavity is isolated from the second cavity, a first protrusion comprising a portion of the semiconductor material is between the first cavity and the second cavity, and the semiconductor material comprises silicon, wherein said removing results in the first cavity or the second cavity, or combinations thereof, to have sidewalls that are formed mainly by {111} planes of silicon crystal of the semiconductor material to be perpendicular, or substantially perpendicular, to a planar surface of the semiconductor material;

performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide;

forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion, wherein the first dielectric material extends at least partially into the first cavity and the second cavity and caps the first cavity and the second cavity to create sealed voids having a lower dielectric constant than the semiconductor material; and

forming at least a portion of an electrically conductive material over at least a portion of the first dielectric material such that the sealed voids provide a reduced capacitance between the electrically conductive material and the semiconductor material.

2. The method of claim 1 , wherein the first dielectric material comprises an oxide.

3. The method of claim 1 , wherein the first protrusion comprises silicon dioxide.

4. The method of claim 1 , wherein a pressure in the first cavity is below atmospheric pressure.

5. The method of claim 1 , further comprising forming at least a portion of an active device is in the semiconductor material.

6. The method of claim 1 , wherein a sidewall of the first cavity is perpendicular to, or substantially perpendicular to, the surface of the semiconductor material.

7. The method of claim 1 , wherein a sidewall of the first cavity is non-perpendicular to the surface of the semiconductor material.

8. The method of claim 1 , wherein a first portion of the semiconductor material has a first orientation and a second portion of the semiconductor material has a second orientation.

9. The method of claim 1 , wherein the orientation-dependent etch is a potassium hydroxide-based (KOH) etch, an ethylene diamine pyrocatechol-based (EDP) etch, a tetramethylammonium hydroxide-based (TMAH) etch, or a hydrazine-based etch.

10. The method of claim 1 , further comprising using wafer bonding to form a second semiconductor coupled to the semiconductor material.

11. The method of claim 1 , further comprising:

forming a second dielectric material over the first dielectric material; and

forming at least a portion of an electrically conductive material over at least a portion of the second dielectric material, wherein the semiconductor material comprises silicon, the semiconductor material comprises one or more epitaxial layers, the first protrusion comprises silicon dioxide, the first dielectric material comprises silicon dioxide, the second dielectric material comprises silicon nitride (Si 3 N 4 ), and the electrically conductive material comprises aluminum, copper, or doped polycrystalline silicon.

12. The method of claim 1 , further comprising planarizing the first dielectric material using a Chemical Mechanical Planarization (“CMP”) process.