IP Library Granted Patent US 10,998,174
Granted Patent B2
US 10,998,174 · App. 12/332,119 · Granted May 4, 2021

Dry etching equipment and method for producing semiconductor device

Inventors: Nobuyuki Kuboi (Tokyo, JP); Tetsuya Tatsumi (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01J37/3299H01J37/32935
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Quick Facts
Patent No.
US 10,998,174
App. No.
12/332,119
Granted
May 4, 2021
Kind
B2
Abstract

A dry etching equipment includes a topography simulator and a control section. The topography simulator controls an amount of deposition species incident upon a sidewall to be processed in accordance with a wafer opening ratio and a solid angle of a local pattern, the deposition amount being represented by a product of a reaction product flux and the solid angle. The control section compares a database obtained by the topography simulator with an actual measured value detected from an etching condition during dry etching to calculate a correction value for etching process, and indicates the correction value to an etching chamber in the dry etching equipment. The dry etching equipment corrects in real time a parameter for the etching process conducted in the etching chamber.

Claims (21)

1. A dry etching equipment comprising:

an etching chamber comprising a semiconductor wafer;

at least one sensor configured to sense at least one plasma condition in the etching chamber during an etching process that etches a pattern into the semiconductor wafer;

a processor; and

a non-transitory memory including instructions, which when executed by the processor, cause the processor to:

calculate a solid angle based on data for the pattern receive the at least one plasma condition from the at least one sensor,

determine, based on the sensed at least one plasma condition, a reaction product flux at a location in the etching chamber above the pattern,

estimate, according to a multiplication of the determined reaction product flux and the calculated solid angle, an amount of deposition species incident upon a sidewall of the pattern,

calculate, based on the estimated amount of deposition species incident upon the sidewall, a correction for at least one process parameter that affects a critical dimension of the pattern, and

control, in real time, the at least one process parameter based on the correction to bring the critical dimension within a predetermined tolerance range.

2. The dry etching equipment according to claim 1 , wherein the at least one plasma condition includes a plasma density, a plasma light-emission intensity, an electron temperature, an ion flux, a radical flux, or an ion energy.

3. The dry etching equipment according to claim 1 , wherein the at least one process parameter includes at least one of a gas pressure, a gas type, a gas flow rate, a source power, a bias power, a top power, and a lower electrode temperature.

4. The dry etching equipment according to claim 3 , wherein the gas type includes a hydrogen bromide gas, an oxygen gas, and a chlorine gas.

5. The dry etching equipment according to claim 4 , wherein the deposition species incident upon the sidewall comprises one or more of SiBr x and SiO x Br y .

6. The dry etching equipment according to claim 1 , wherein the instructions cause the processor to estimate an etching rate and a deposition rate based on the amount of deposition species incident upon the sidewall.

7. The dry etching equipment according to claim 6 , wherein the instructions cause the processor to estimate progress of the etching process based on the etching rate and the deposition rate.

8. The dry etching equipment according to claim 7 , wherein the instructions cause the processor to determine that the etching process is complete based on the estimated progress of the etching process.

9. The dry etching equipment according to claim 1 , wherein the instructions cause the processor to:

terminate the etching process upon determining that the etching process is complete.

10. The dry etching equipment according to claim 9 , wherein the instructions cause the processor to:

upon termination of the etching process, measure at least one of the critical dimension, a taper angle, and a photoresist residue amount.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040716/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: KUBOI, NOBUYUKI; TATSUMI, TETSUYA
To: SONY CORPORATION
Reel/Frame 021970/0641 →
Priority Claims (1)
JP JP2007-326966 · Dec 19, 2007 · national
Continuity (1)
Related Publication 20090162950A1 · Jun 25, 2009