Method for manufacturing printed circuit board

1. A method for manufacturing printed circuit boards, comprising:

providing a printed circuit board substrate including a metal-clad substrate and multiple spaced circuit substrates, {M i }, i=1, 2, . . . , N, N being an integer greater than 2, the circuit substrates, {M i }, mounted on the metal-clad substrate along an imaginary circle, the circuit substrates being equiangularly arranged about the center of the circle, the i+1th circuit substrate, M i+1 , being oriented 360/N degrees with respect to the ith neighboring circuit substrate, M i ;

defining multiple processing regions, {K i }, i=1, 2, . . . , N, N being an integer greater than 2, on the metal-clad substrate, the processing regions, {K i }, spatially corresponding to the respective circuit substrates, {M i };

forming a photoresist layer on an opposite side of the metal-clad substrate to the circuit substrates, the photoresist layer including multiple photoresist layer sections, {P i }, i=1, 2, . . . , N, N being an integer greater than 2, the photoresist layer sections, {P i }, respectively located at the processing regions, {K i };

exposing the ith photoresist layer section, P i , which spatially corresponds to the ith circuit substrate, M i ;

rotating the printed circuit board substrate an angle of 360/N degrees about the center of the circle;

exposing the i+1th photoresist layer section, P i+1 , which is proximate to the ith photoresist layer section, P i , and spatially corresponds to the i+1th circuit substrate, M i+1 ;

developing the ith photoresist layer section, P i ;

etching the metal-clad substrate at the i+1th processing region, K i+1 , to form electrically conductive patterns thereon;

developing the i+1th photoresist layer section, P i+1 ; and

etching the metal-clad substrate at the i+1th processing region, K i+1 , to form electrically conductive patterns thereon;

wherein the ith and i+1th photoresist layer sections, P i , and P i+1 , are formed simultaneously; but the ith photoresist layer section, P i , is exposed prior to that of the i+1th photoresist layer section, P i+1 .

2. The method as claimed in claim 1 , wherein the metal-clad substrate includes a first insulation layer and a first electrically conductive layer, the photoresist layer is formed on the first electrically conductive layer of the metal-clad substrate, and the circuit substrates, {M i }, are mounted on the first insulation layer of the metal-clad substrate.

3. The method as claimed in claim 1 , wherein the ith photoresist layer section, P i , is exposed prior to the step of developing the ith photoresist layer section, P i .

4. The method as claimed in claim 1 , wherein the ith photoresist layer section, P i , is developed prior to the step of etching the metal-clad substrate at the ith processing region, K i .

5. The method as claimed in claim 1 , wherein the ith photoresist layer section, P i , and the i+1th photoresist layer section, P i+1 , are developed simultaneously.

6. The method as claimed in claim 1 , wherein the metal-clad substrate at the ith processing region, K i , and at the i+1th processing region, K i+1 , is etched simultaneously.

7. The method as claimed in claim 1 , wherein the printed circuit board substrate is rotated an angle of 360/N degrees about the center of the circle prior to exposing the i+1th photoresist layer section, P i+1 .

8. The method as claimed in claim 1 , wherein the printed circuit board substrate is rotated an angle of 360/N degrees about the center of the circle after exposing the i+1th photoresist layer section, P i+1 .

9. The method as claimed in claim 1 , further comprising:

cutting the printed circuit board substrate along imaginary boundary lines between the multiple processing regions, {K i }, to form multiple printed circuit boards, wherein the multiple printed circuit boards have a same structure.

10. The method as claimed in claim 9 , further comprising:

forming coverlayers on the multiple printed circuit boards to protect the electrically conductive patterns formed in processes of etching of the metal-clad substrate at the multiple processing regions, {K i }.

11. The method as claimed in claim 1 , wherein the circuit substrates have an identical structure.