Memory programming method and data access method

1. A memory programming method for a NAND flash with a plurality of multi level cells, comprising:

performing a first programming operation to program the multi level cell from an initial state to a first target state, which corresponds to a first storage data and has a first threshold voltage range, wherein the first threshold voltage range is between a first voltage and a second voltage larger than the first voltage;

setting a flag bit of the NAND flash to a first state to indicate that the first programming operation has been performed;

performing a second programming operation to program the multi level cell from the first target state to a second target state, which corresponds to the first storage data and has a second threshold voltage range, wherein the second threshold voltage range is between the second voltage and a third voltage larger than the second voltage; and

setting the flag bit to a second state to indicate that the second programming operation has been performed.

2. The memory programming method as claimed in claim 1 , further comprising:

programming the multi level cell from the second target state to a third target state, which corresponds to a second storage data and has a third threshold voltage range, wherein the third threshold voltage range is between the third voltage and a maximum threshold voltage larger than the third voltage.

3. The memory programming method as claimed in claim 2 , further comprising:

programming the multi level cell from the initial state to a fourth target state, which corresponds to a third storage data and has a fourth threshold voltage range, wherein the fourth threshold voltage range is between the first voltage and the second voltage.

4. The memory programming method as claimed in claim 3 , wherein the initial state corresponds to a fourth storage data and has a fifth threshold voltage range, wherein the first, second, third and fourth storage data are a two-bit data with logic state ‘10’, ‘00’, ‘01’ and ‘11’ respectively, and the fifth threshold voltage range is between a minimum threshold voltage and the first voltage larger than the minimum threshold voltage.

5. The memory programming method as claimed in claim 4 , wherein the first programming operation is performed to store a least significant bit of the two-bit data into the multi level cell, and the least significant bit corresponds to a first address.

6. The memory programming method as claimed in claim 5 , wherein the second programming operation is performed to store a most significant bit of the two-bit data into the multi level cell, and the most significant bit corresponds to a second address, wherein the first address and the second address are located on different pages of the NAND flash.

7. A data accessing method for a NAND flash with a plurality of multi level cells, comprising:

performing a first programming operation to program the multi level cell from an initial state to a first target state, which corresponds to a first logic state of a two-bit data and has a first threshold voltage range, wherein the first threshold voltage range is between a first voltage and a second voltage larger than the first voltage;

setting a flag bit of the NAND flash to a first state to indicate that the first programming operation has been performed;

performing a second programming operation to program the multi level cell from the first target state to a second target state, which corresponds to the first logic state and has a second threshold voltage range, wherein the second threshold voltage range is between the second voltage and a third voltage larger than the second voltage;

setting the flag bit to a second state to indicate that the second programming operation has been performed;

performing a reading operation to obtain a read threshold voltage of the multi level cell; and

determining a logic state of the two-bit data stored in the multi level cell according to the read threshold voltage and the flag bit.

8. The data accessing method as claimed in claim 7 , further comprising:

programming the multi level cell from the second target state to a third target state, which corresponds to a second logic state of the two-bit data and has a third threshold voltage range, wherein the third threshold voltage range is between the third voltage and a maximum threshold voltage larger than the third voltage.

9. The data accessing method as claimed in claim 8 , further comprising:

programming the multi level cell from the initial state to a fourth target state, which corresponds to a third logic state of the two-bit data and has a fourth threshold voltage range, wherein the fourth threshold voltage range is between the first voltage and the second voltage.

10. The data accessing method as claimed in claim 9 , wherein the initial state corresponds to a fourth logic state of the two-bit data and has a fifth threshold voltage range, wherein the first, second, third and fourth logic states are ‘10’, ‘00’, ‘01’ and ‘11’ respectively, and the fifth threshold voltage range is between a minimum threshold voltage and the first voltage larger than the minimum threshold voltage.

11. The data accessing method as claimed in claim 10 , wherein the first programming operation is performed to store a least significant bit of the two-bit data into the multi level cell, and the least significant bit corresponds to a first address.

12. The data accessing method as claimed in claim 10 , wherein the second programming operation is performed to store a most significant bit of the two-bit data into the multi level cell, and the most significant bit corresponds to a second address, wherein the first address and the second address are located on different pages of the NAND flash.

13. The data accessing method as claimed in claim 10 , wherein the step of determining the logic state of the two-bit data further comprises:

determining the logic state of the two-bit data is ‘11’ when the read threshold voltage is smaller than the first voltage.

14. The data accessing method as claimed in claim 10 , wherein the step of determining the logic state of the two-bit data further comprises:

determining the logic state of the two-bit data is ‘10’ when the read threshold voltage is between the second voltage and the third voltage.

15. The data accessing method as claimed in claim 10 , wherein the step of determining the logic state of the two-bit data further comprises:

determining the logic state of the two-bit data is ‘00’ when the read threshold voltage is larger than the third voltage.

16. The data accessing method as claimed in claim 10 , wherein the step of determining the logic state of the two-bit data further comprises:

determining the logic state of the two-bit data is ‘10’ when the read threshold voltage is between the first voltage and the second voltage and the flag bit is in the first state; and

determining the logic state of the two-bit data is ‘01’ when the read threshold voltage is between the first voltage and the second voltage and the flag bit is in the second state.