IP Library Granted Patent US 8,035,315
Granted Patent B2
US 8,035,315 · App. 12/340,985 · Granted Oct 11, 2011

LED driver with feedback calibration

Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,035,315
App. No.
12/340,985
Granted
Oct 11, 2011
Kind
B2
Abstract

Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive a plurality of LED strings. An LED driver implements a feedback mechanism to monitor the tail voltages of the active LED strings to identify the minimum tail voltage and adjust the output voltage of the voltage source based on the lowest tail voltage. A loop calibration module of the LED driver calibrates the feedback mechanism of the LED driver based on a relationship between a digital code value used to generate a particular output voltage and another digital code value generated based on the minimum tail voltage resulting from the particular output voltage.

Claims (76)

1. A method comprising:

generating a first voltage based on a first digital code value;

providing a second voltage to a head end of each of a plurality of light emitting diode (LED) strings, each LED string having a corresponding tail voltage responsive to the second voltage, and the second voltage based on the first voltage;

determining a second digital code value representative of a first minimum tail voltage of the plurality of LED strings responsive to the second voltage;

determining a feedback compensation factor based on a relationship between the first digital code value and the second digital code value;

determining a third digital code value based on the feedback compensation factor;

generating a third voltage based on the third digital code value; and

providing a fourth voltage to the head end of each of the plurality of LED strings, the fourth voltage based on the third voltage.

2. The method of claim 1 , further comprising:

determining a fourth digital code value representative of a second minimum tail voltage of the plurality of LED strings responsive to the fourth voltage;

determining a fifth digital code value based on the fourth digital code value and the feedback compensation factor;

generating a fifth voltage based on the fifth digital code value; and

providing a sixth voltage to the head end of each of the plurality of LED strings, the sixth voltage based on the fifth voltage.

3. The method of claim 1 , wherein:

generating the first voltage comprises generating the first voltage via a digital-to-analog converter (DAC);

determining the second digital code value comprises determining the second digital code value via an analog-to-digital converter (ADC); and

generating the third voltage comprises generating the third voltage via the DAC.

4. The method of claim 3 , wherein:

providing the second voltage comprises generating the second voltage based on a relationship between the first voltage and a first voltage output of a voltage divider;

providing the fourth voltage comprises generating the fourth voltage based on a relationship between the third voltage and a second voltage output of the voltage divider; and

wherein the DAC and the ADC are configured based on an expected resistance ratio of the voltage divider.

5. The method of claim 4 , wherein the feedback compensation factor compensates for a difference between the expected resistance ratio and an actual resistance ratio of the voltage divider.

6. The method of claim 1 , further comprising:

the relationship between the first digital code value and the second digital code value comprises a ratio of the first digital code value and the second digital code value; and

determining the feedback compensation factor comprises determining the feedback compensation factor based on a difference between the ratio and an expected ratio.

7. The method of claim 1 , further comprising:

generating the first digital code value based on a predetermined increase from a fourth digital code value, wherein the relationship between the first digital code value and the second digital code value comprises a ratio of the second digital code value and a difference between the first digital code value and the fourth digital code value; and

determining the feedback compensation factor comprises determining the feedback compensation factor based on a difference between the ratio and an expected ratio.

8. The method of claim 1 , further comprising:

operating a LED panel comprising the plurality of LED strings in a start-up mode and an operational mode, wherein image content is displayed via the LED panel in the operational mode; and

wherein:

generating the first voltage comprises generating the first voltage in the start-up mode;

providing the second voltage comprises providing the second voltage in the start-up mode;

determining the second digital code value comprises determining the second digital code value in the start-up mode;

determining the feedback compensation factor comprises determining the feedback compensation factor in the operational mode;

determining the third digital code value comprises determining the third digital code value in the operational mode;

generating the third voltage comprises generating the third voltage in the operational mode; and

providing the fourth voltage comprises providing the fourth voltage in the operational mode.

9. The method of claim 1 , further comprising:

operating a LED panel comprising the plurality of LED strings in a start-up mode and an operational mode, wherein image content is displayed via the LED panel in the operational mode; and

wherein:

generating the first voltage comprises generating the first voltage in the operational mode;

providing the second voltage comprises providing the second voltage in the operational mode;

determining the second digital code value comprises determining the second digital code value in the operational mode;

determining the feedback compensation factor comprises determining the feedback compensation factor in the operational mode;

determining the third digital code value comprises determining the third digital code value in the operational mode;

generating the third voltage comprises generating the third voltage in the operational mode; and

providing the fourth voltage comprises providing the fourth voltage in the operational mode.

10. The method of claim 9 , wherein determining the feedback compensation factor comprises determining the feedback compensation factor responsive to determining that a utilization of LED strings of the plurality of LED strings has remained constant between generating the first voltage and determining the second digital code value.

11. The method of claim 10 , further comprising:

monitoring a duty cycle of a pulse width modulation (PWM) data used to control the LED strings to determine whether the utilization of LED strings has remained constant.

12. A system comprising:

a light emitting diode (LED) driver comprising:

a plurality of tail inputs, each tail input configured to couple to a tail end of a corresponding one of a plurality of light emitting diode (LED) strings; and

a feedback controller comprising:

an analog-to-digital converter (ADC) configured to generate digital code values representative of corresponding minimum tail voltages of the plurality of LED strings;

a code processing module configured to, in a first mode, generate digital code values based on the digital code values generated by the ADC;

a digital-to-analog converter (DAC) configured to generate voltages based on the digital code values generated by the code processing module;

a loop calibration module configured to generate a feedback compensation factor based on a relationship between a digital code value generated by the code processing module and a resulting digital code value generated by the ADC; and

the code processing module is configured to, in a second mode, generate digital code values based on digital code values generated by the ADC and based on the feedback compensation factor.

13. The system of claim 12 , further comprising:

a voltage source configured to adjust an output voltage provided to a head end of each of the plurality of LED strings based on the voltages generated by the DAC.

14. The system of claim 13 , further comprising:

a voltage divider configured to generate a voltage based on the output voltage of the voltage source;

wherein the voltage source is configured to adjust the output voltage based on a relationship between the voltage generated by the voltage divider and a voltage generated by the DAC; and

wherein the DAC and the ADC are configured based on an expected resistance ratio of the voltage divider.

15. The system of claim 14 , wherein the feedback compensation factor compensates for a difference between the expected resistance ratio and an actual resistance ratio of the voltage divider.

16. The system of claim 12 , wherein:

a relationship between the digital code value generated by the code processing module and the resulting digital code value generated by the ADC comprises a ratio of the digital code value generated by the code processing module and the resulting digital code value generated by the ADC; and

the loop calibration module is configured to determine the feedback compensation factor based on a difference between the ratio and an expected ratio.

17. The system of claim 12 , wherein the loop calibration module is configured to determine the feedback compensation factor during a start-up mode.

18. The system of claim 12 , wherein the loop calibration module is configured to determine the feedback compensation factor during an operational mode responsive to determining that a utilization of LED strings of the plurality of LED strings has remained constant between generation of the digital code value by the DAC and generation of the resulting digital code value by the ADC.

19. The system of claim 18 , further comprising:

a data/timing control module configured to monitor a duty cycle of a pulse width modulation (PWM) data used to control the LED strings to determine whether the utilization of LED strings has remained constant.

20. The system of claim 12 , further comprising:

a LED panel comprising the plurality of LED strings.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 12, 2009
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2008
From: ZHAO, BIN; CORNISH, JACK W.; HORNG, BRIAN B.; KAMEYA, ANDREW M.; KRELLNER, JAN; KWOK, KENNETH C.; LEE, VICTOR K.; XIN, WEIZHUANG W.
To: FREESCALE SEMICONDUCTOR, INC.
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Continuity (1)
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