IP Library Granted Patent US 7,981,746
Granted Patent B2
US 7,981,746 · App. 12/341,874 · Granted Jul 19, 2011

Semiconductor device and method for manufacturing thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,981,746
App. No.
12/341,874
Granted
Jul 19, 2011
Kind
B2
Abstract

The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof.

Claims (30)

1. A method for manufacturing a semiconductor device, the method comprising:

forming a trench section in a semiconductor substrate;

forming a tunnel insulating film that covers an inner surface of the trench section;

forming a first conductive layer in the trench section so as to be in contact with the tunnel insulating film at a lower portion of the trench section, and so as to make the tunnel insulating film exposed at an upper portion of the trench section;

forming a trap layer and a top insulating film sequentially on the first conductive layer, and in contact with the upper portion of the trench section;

removing the trap layer and the top insulating film formed on the first conductive layer at a center portion of the trench section in the width direction;

forming a second conductive layer on the first conductive layer at the center portion of the trench section in the width direction and on the top insulating film; and

forming a gate electrode from the first conductive layer and the second conductive layer.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conductive layer is formed so that an upper surface of the first conductive layer becomes higher at the center portion of the trench section in the width direction than an upper surface of the semiconductor substrate.

3. The method for manufacturing a semiconductor device according to claim 1 , the method further comprising:

forming a third conducive layer so as to be in contact with the entire tunnel insulating film in the trench section, and so as to be higher than the upper surface of the semiconductor substrate; wherein the forming of the first conductive layer comprises etching the third conductive layer.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein the etching of the third conductive layer may be through isotropical etching.

5. The method for manufacturing a semiconductor device according to claim 3 , wherein the third conductive layer may be formed by using a first mask layer that is used to form the trench section.

6. The method for manufacturing a semiconductor device according to claim 3 , the method further comprising:

forming a second mask layer defined by the trench section on the third conductive layer.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the etching of the third conductive layer may be performed by etching using the second mask layer.

8. The method for manufacturing a semiconductor device according to claim 1 , the method further comprising:

forming a fourth conductive layer on the top insulating film formed on the first conductive layer; wherein removing the trap layer and the top insulating film at the center portion of the trench section in the width direction comprises polishing the fourth conductive layer, the trap layer and the top insulating film at the center portion of the trench section in the width direction, and the first conductive layer at the center portion of the trench section in the width direction.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein forming the second conductive layer comprises:

forming a fifth conductive layer on the first conductive layer and the fourth conductive layer; and

forming the second conductive layer out of the fourth conductive layer and the fifth conductive layer.

10. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conductive layer is formed so that the upper surface of the first conductive layer becomes lower than the upper surface of the semiconductor substrate.

11. The method for manufacturing a semiconductor device according to claim 10 , the method further comprising:

forming a sixth conductive layer on each side wall of the top insulating film provided on both sides of the trench section at the upper portion of the trench section; wherein removing the trap layer and the top insulating film at the center portion of the trench section in the width direction comprises:

removing the trap layer and the top insulating film by using the sixth conductive layer as a mask.

12. The method for manufacturing a semiconductor device according to claim 11 , further comprising:

forming a seventh conductive layer in between the sixth conductive layers; wherein the forming of the second conductive layer comprises:

forming the fifth conductive layer on the sixth conductive layer and the seventh conductive layer; and forming the second conductive layer out of the sixth conductive layer, the seventh conductive layer, and the fifth conductive layer.

13. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

forming an isolation trench in the semiconductor substrate.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0337 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2009
From: TOYAMA, FUMIAKI; INOUE, FUMIHIKO
To: SPANSION LLC
Reel/Frame 022252/0135 →