Apparatus for testing memory device
View Patent ↗Embodiments relate to an apparatus that may test a memory device. According to embodiments, a period of memory development may be reduced in a manner of testing a delay of a major part in a memory by adding a simple circuit without using expensive equipment and by which a memory development cost can be lowered. According to embodiments, a memory device may include a memory array and a redundancy memory. According to embodiments, a device may include a programmable redundancy decoder determining a drive force to corresponding to a selection signal, the programmable redundancy decoder outputting the determined drive force to a word line of the redundancy memory and a delay difference generating unit generating a delay difference signal corresponding to a delay difference between first and second word line signals outputted from the redundancy memory.
1. A device, comprising:
a memory array and a redundancy memory;
a programmable redundancy decoder configured to determine a drive force corresponding to a selection signal, the programmable redundancy decoder configured to output the determined drive force to a word line of the redundancy memory; and
a delay difference generating unit configured to generate a delay difference signal corresponding to a delay difference between first and second word line signals outputted from the redundancy memory.
2. The device of claim 1 , wherein the programmable redundancy decoder is configured to determine 2 n drive forces differing from each other, wherein n is a bit number of the selection signal.
3. The device of claim 2 , wherein the programmable redundancy decoder comprises:
first through 2 nth inverters serially connected to upper and lower transistors of opposite types, the first through 2 nth inverters connected in common to each other via contact points of the upper and lower transistors to output the drive force; and
a logic combination unit configured to perform a logic combination on bits of the selection signal to output to the first through 2 nth inverters,
wherein the first inverter operates in response to a test signal.
4. The device of claim 3 , wherein the upper transistor comprises a PMOS transistor, and wherein the lower transistor comprises an NMOS transistor.
5. The device of claim 3 , wherein n=2.
6. The device of claim 5 , wherein the logic combination unit comprises:
an inverse OR operation unit configured to perform an inverse OR operation on lower and upper bits of the selection signal to output to the second inverter;
a first inverting unit configured to invert the lower bit to output to the third inverter;
a first inverse AND operation unit configured to perform an inverse AND operation on the lower and upper bits to output to the fourth inverter; and
an AND operation unit configured to perform an AND operation on outputs of the inverse OR operation unit, the first inverting unit and the first inverse AND operation unit, and configured to output an AND operated result to the first through fourth inverters.
7. The device of claim 1 , wherein the first word line signal is outputted from a point of the word line of the redundancy memory located closest to the programmable redundancy decoder, and wherein the second word line signal is outputted from a point of the word line located farthest from the programmable redundancy decoder.
8. The device of claim 1 , wherein the delay difference generating unit comprises a first phase/frequency detector configured to measure an ascending delay difference of phase and frequency between the first and second word line signals, and output the measured ascending delay difference as the delay difference signal.
9. The device of claim 8 , wherein the first phase/frequency detector comprises:
a first inverse AND operation unit configured to perform an inverse AND operation on an inverted first word line signal and a first result signal;
a second inverse AND operation unit configured to perform an inverse AND operation on an output of the first inverse AND operation unit and a second result signal;
a third inverse AND operation unit configured to perform an inverse AND operation on an output of the second inverse AND operation unit and a third result signal to output the second result signal;
a fourth inverse AND operation unit configured to perform an inverse AND operation on the third and fourth result signals;
a fifth inverse AND operation unit configured to perform an inverse AND operation on an output of the fourth inverse AND operation unit and a fifth result signal to output the fourth result signal;
a sixth inverse AND operation unit configured to perform an inverse AND operation on an inverted second word line signal and the ascending delay difference to output the fifth result signal;
a seventh inverse AND operation unit configured to perform an inverse AND operation on outputs of the first and second inverse AND operation units and the third result signal to output the first result signal;
an eighth inverse AND operation unit configured to perform an inverse AND operation on the third, fourth, and fifth result signals to output the ascending delay difference; and
a ninth inverse AND operation unit configured to perform an inverse AND operation on outputs of the first and second inverse AND operation units and the fourth and fifth result signals to output the third result signal.
10. The device of claim 9 , wherein the logic combination unit comprises:
an inverse OR operation unit configured to perform an inverse OR operation on lower and upper bits of the selection signal to provide an output to a first inverter;
a first inverting unit configured to invert the lower bit to provide an output to a second inverter;
a tenth inverse AND operation unit configured to perform an inverse AND operation on the lower and upper bits to provide an output to a third inverter; and
an AND operation unit configured to perform an AND operation on outputs of the inverse OR operation unit, a fourth inverting unit and the tenth inverse AND operation unit, the AND operation unit outputting the AND operated results to the first through fourth inverters.
11. The device of claim 10 , wherein the programmable redundancy decoder is configured to determine 2 n drive forces differing from each other, wherein n is a bit number of the selection signal.
12. The device of claim 8 , wherein the delay difference generating unit comprises a second phase/frequency detector configured to measure a descending delay difference of phase and frequency between an inverted first word line signal and an inverted second word line signal and output the measured descending delay difference as the delay difference signal.
13. The device of claim 12 , wherein the second phase/frequency detector comprises:
a first inverse AND operation unit configured to perform an inverse AND operation on the first word line signal and the descending delay difference;
a second inverse AND operation unit configured to perform an inverse AND operation on an output of the first inverse AND operation unit and a first result signal;
a third inverse AND operation unit configured to perform an inverse AND operation on an output of the second inverse AND operation unit and a second result signal to output the first result signal;
a fourth inverse AND operation unit configured to perform an inverse AND operation on the second and third result signals;
a fifth inverse AND operation unit configured to perform an inverse AND operation on an output of the fourth inverse AND operation unit and a fourth result signal to output the third result signal;
a sixth inverse AND operation unit configured to perform an inverse AND operation on the second word line signal and a fifth result signal to output the fourth result signal;
a seventh inverse AND operation unit configured to perform an inverse AND operation on outputs of the first and second inverse AND operation units and the second result signal to output as the descending delay difference;
an eighth inverse AND operation unit configured to perform an inverse AND operation on the second and third result signals to output the fifth result signal; and
a ninth inverse AND operation unit configured to perform an inverse AND operation on outputs of the first and second inverse operation units and the third and fourth result signals to output the second result signal.
14. The device of claim 13 , wherein the logic combination unit comprises:
an inverse OR operation unit configured to perform an inverse OR operation on lower and upper bits of the selection signal to output to a first inverter;
a first inverting unit configured to invert the lower bit to output to a second inverter;
a tenth inverse AND operation unit configured to perform an inverse AND operation on the lower and upper bits to output to a third inverter; and
an AND operation unit configured to perform an AND operation on outputs of the inverse OR operation unit, the tenth inverting unit and the first inverse AND operation unit, the AND operation unit outputting the AND operated results to the first through fourth inverters.
15. The device of claim 14 , wherein the programmable redundancy decoder is capable of determining 2 n drive forces differing from each other, wherein n is a bit number of the selection signal.
16. A method, comprising:
providing a memory array and a redundancy memory;
determining a drive force corresponding to a selection signal using a programmable redundancy decoder and outputting the determined drive force from the programmable redundancy decoder to a word line of the redundancy memory; and
generating a delay difference signal corresponding to a delay difference between first and second word line signals outputted from the redundancy memory using a delay difference generating unit.
17. The method of claim 16 , comprising determining 2 n drive forces differing from each other by the programmable redundancy decoder, wherein n is a bit number of the selection signal.
18. The method of claim 17 , wherein the programmable redundancy decoder comprises:
first through 2 nth inverters serially connected to upper and lower transistors of opposite types, the first through 2 nth inverters connected in common to each other via contact points of the upper and lower transistors to output the drive force; and
a logic combination unit configured to perform a logic combination on bits of the selection signal to output to the first to 2nth inverters,
wherein the first inverter operates in response to a test signal.
19. The method of claim 18 , wherein the upper transistor comprises a PMOS transistor and wherein the lower transistor comprises an NMOS transistor.
20. The method of claim 18 , wherein the programmable redundancy decoder comprises first, second, third, and fourth inverters, and wherein the logic combination unit comprises:
an inverse OR operation unit configured to perform an inverse OR operation on lower and upper bits of the selection signal to output to the second inverter;
a first inverting unit configured to invert the lower bit to output to the third inverter;
a first inverse AND operation unit configured to perform an inverse AND operation on the lower and upper bits to output to the fourth inverter; and
an AND operation unit configured to perform an AND operation on outputs of the inverse OR operation unit, the first inverting unit and the first inverse AND operation unit, the AND operation unit outputting the AND operated results to the first to fourth inverters.