Semiconductor chip package and method for manufacturing thereof
View Patent ↗A semiconductor chip package and a method for manufacturing thereof includes sequentially forming upper dielectric layer patterns and lower dielectric patterns over a substrate to expose an underlying metal line such that the lower dielectric layer patterns overlap the metal line, positioning a solder ball over and contacting the lower dielectric layer patterns such that the solder ball does not contact the metal line, and then placing the solder ball in a contacting position over the metal line by performing an etching process on the lower dielectric layer patterns. Therefore, no cracks occur on the chip pads so that there is no concern of short phenomenon generated in the terminal.
1. A method comprising:
forming a chip pad including a substrate; and then
forming a metal line in the substrate; and then
forming a multi-layer dielectric layer pattern over the substrate including a first dielectric layer pattern formed over and overlapping the metal line and a second dielectric layer pattern formed over the first dielectric layer pattern to expose the metal line; and then
placing a solder ball over the metal line to contact corner edge portions of the first dielectric layer pattern but not contact the metal line; and then
etching the corner edge portions of the first dielectric layer pattern such that the solder ball contacts the metal line.
2. The method of claim 1 , wherein etching the corner edge portions comprises etching the corner edge portions such to have rounded cross-sections.
3. The method of claim 1 , wherein forming the multi-layer dielectric layer pattern comprises:
forming a first dielectric layer over the substrate including the metal line; and then
planarizing the first dielectric layer; and then
forming a second dielectric layer over the first dielectric layer; and then
selectively etching the first and second dielectric layers to expose the metal line.
4. The method of claim 3 , wherein the first dielectric layer is selectively etched by a wet etching process using the second dielectric layer as a mask.
5. The method of claim 3 , wherein the first dielectric layer is composed of an oxide film.
6. The method of claim 3 , wherein the second dielectric layer is composed of a nitride film.
7. The method of claim 3 , wherein selectively etching the first and second dielectric layers comprises forming a first opening in the first dielectric layer exposing the metal line and a second opening in the second dielectric layer exposing the metal line such that the first opening has a width less than the width of the second opening.
8. The method of claim 7 , wherein the width of the second opening is the same as the width of the metal line.
9. The method of claim 7 , wherein the width of the first opening is less than the diameter of the solder ball.
10. The method of claim 1 , wherein the metal line is composed of aluminum (Al).
11. A method comprising:
forming a metal line in a substrate; and then
sequentially forming upper dielectric layer patterns and lower dielectric patterns over the substrate to expose the metal line such that the lower dielectric layer patterns overlap the metal line; and then
positioning a solder ball over and contacting the lower dielectric layer patterns such that the solder ball does not contact the metal line; and then
placing the solder ball in a contacting position over the metal line by performing an etching process on the lower dielectric layer patterns.
12. The method of claim 11 , wherein sequentially forming upper dielectric layer patterns and lower dielectric patterns comprises:
forming a lower dielectric layer over the substrate including the metal line; and then
planarizing the lower dielectric layer; and then
forming an upper dielectric layer over the lower dielectric layer; and then
forming the upper dielectric patterns by performing a first etching process on the upper dielectric layer; and then
forming the lower dielectric patterns by performing a second etching process on the lower dielectric layer.
13. The method of claim 12 , wherein the second etching process is a wet etching process and the wet etching process is performed using the upper dielectric layer patterns as masks.