Granted Patent B2

US 8,373,953 · App. 12/345,507 · Granted Feb 12, 2013

Abstract

Claims (35)

1. A semiconductor device comprising:

a plurality of bumps arranged on a surface of a semiconductor device;

a plurality of electrostatic discharge (ESD) protection cells, wherein individual ESD protection cells couple to and are downstream of individual bumps, the plurality of ESD protection cells are co-located in groups to form at least one ESD cluster located within an interior region of a major side of the semiconductor device, the interior region away from a perimeter of the major side of the semiconductor device, the ESD clusters autarchically located with respect to the bumps, analog functional modules, and the perimeter of the major side of the semiconductor device;

a plurality of analog functional modules wherein the analog functional modules couple to and are downstream of individual ESD protection cells, the ESD protection cells operable to protect circuits within the analog functional modules from ESD; and the ESD protection cells are placed proximate to communicatively coupled bumps and analog functional modules;

a first power supply bus and a second power supply bus; the plurality of ESD protection cells are coupled to the first and second power supply buses; and

a rail clamp coupled between the first and second power supply buses, the rail clamp provides an ESD discharge path between the first and second power supply buses.

2. The semiconductor device of claim 1 , wherein a plurality of rail clamps is coupled between the first and second power supply buses; the rail clamps work in parallel to provide an ESD discharge path between the first and second power supply buses.

3. The semiconductor device of claim 2 , wherein individual ESD cells comprise rail clamps.

4. The semiconductor device of claim 1 , wherein at least one of the analog functional modules comprise an analog I/O circuit.

5. The semiconductor device of claim 1 , wherein the ESD protection cell location reduces signal routing length to the bumps.

6. The semiconductor device of claim 1 , wherein the semiconductor device comprises a flip chip.

7. The semiconductor device of claim 1 , wherein ESD protection cells within an ESD cluster are abutted.

8. The semiconductor device of claim 1 , wherein ESD protection cell clusters are located between functional modules within the semiconductor device.

9. The semiconductor device of claim 1 , wherein ESD protection cells within at least one ESD cluster are abutted to form linear ESD protection cell segments.

10. A semiconductor device comprising:

a plurality of bumps located on a surface of the semiconductor device;

a plurality of electrostatic discharge (ESD) protection cells, wherein individual ESD protection cells couple to and are downstream of individual bumps, the plurality of ESD protection cells are co-located in groups to form at least one ESD cluster located within an interior region of a major side of the semiconductor device, the interior region away from a periphery of a die of the semiconductor device;

a plurality of analog circuitry modules, wherein each of the plurality of analog circuitry modules is coupled to an is downstream of an ESD protection cell of the plurality of ESD protection cells, the ESD protection cells operable to protect the plurality of analog circuit modules from ESD;

a first power supply bus and a second power supply bus, the plurality of ESD protection cells are coupled to the first and second power supply buses; and

a rail clamp coupled between the first and second power supply buses, the rail clamp provides an ESD discharge path between the first and second power supply buses.

11. The semiconductor device of claim 10 , wherein a plurality of rail clamps is coupled between the first and second power supply buses; the rail clamps work in parallel to provide an ESD discharge path between the first and second power supply buses.

12. The semiconductor device of claim 11 , wherein the plurality of rail clamps are implemented in the plurality of ESD cells.

13. The semiconductor device of claim 10 , wherein at least one of the analog circuitry comprises an analog I/O circuit.

14. The semiconductor device of claim 10 , wherein the semiconductor device comprises a flip chip.

15. The semiconductor device of claim 10 , wherein ESD protection cell clusters are located between functional modules within the semiconductor device.

16. The semiconductor device of claim 10 , wherein ESD protection cells within at least one ESD cluster are abutted to form linear ESD protection cell segments.

17. The semiconductor device of claim 10 , wherein ESD protection cells within an ESD cluster are abutted.

18. A layout method of a semiconductor device, comprising:

arranging a location of a plurality of bumps along a major surface of the semiconductor device;

arranging a location of a plurality of analog functional modules wherein analog functional modules couple to and are downstream of individual electrostatic discharge (ESD) protection cells, the ESD protection cells operable to protect circuits within the functional module from electrostatic discharge; and

arranging a location of groups of individual ESD protection cells to form ESD clusters, the ESD clusters located within an interior region of a major side of the semiconductor device, the interior region away from a periphery of the major side of the semiconductor device, and proximate to communicatively coupled bumps and analog functional modules.

19. The layout method of claim 18 wherein ESD protection cells within an ESD cluster are abutted to form linear ESD protection cell segments.

20. The layout method of claim 18 wherein the plurality of ESD protection cells comprise:

a first set of ESD protection cells; and

a second set of ESD protection cells, the first set of ESD protection cells is larger than the second set of ESD protection cells.

Assignments (18)