Method of forming contact
View Patent ↗A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.
1. A fabrication method of a contact, the method comprising:
providing a substrate having at least two metal oxide semiconductor devices of a same conductive type already formed thereon, wherein the two metal oxide semiconductor devices comprise a gap therebetween;
forming a first stress layer over the substrate to cover the two metal oxide semiconductors, wherein the first stress layer is formed by:
forming a stress material layer over the substrate to cover the two metal oxide semiconductor devices and to fill the gap, wherein the stress material layer inside the gap comprises a seam; and
performing an etching process to remove a portion of the stress material layer inside the gap to expand a width of the seam;
forming a second stress layer on the first stress layer, wherein the first stress layer and the second stress layer provides a same type of stress;
forming a dielectric layer on the second stress layer;
removing a portion of the dielectric layer, a portion of the first stress layer and a portion of the second stress layer inside the gap to expose a portion of a surface of the substrate to form a contact opening; and
filling a conductive layer in the contact opening.
2. The method of claim 1 , wherein before the step of forming the second stress layer, the step of forming the first stress layer is repeated for at least one time.
3. The method of claim 1 , wherein a material of the stress material layer comprises silicon nitride.
4. The method of claim 1 , wherein the step in forming the stress material layer comprises performing plasma enhanced chemical vapor deposition.
5. The method of claim 1 , wherein a material of the second stress layer comprises silicon nitride.
6. The method of claim 1 , wherein the step in forming the second stress material comprises performing plasma enhanced chemical vapor deposition.
7. The method of claim 1 , wherein a total thickness of the first stress layer and the second stress layer is about 150 to 1500 angstroms.
8. The method of claim 1 , wherein the etching back process includes a dry etching process or a wet etching process.
9. The method of claim 1 , wherein a material in constituting the dielectric layer is selected from the group consisting of silicon oxide, phosphorous silicon glass, boron silicon glass, boron phosphorous silicon glass and undoped silicon glass/phosphorous silicon glass.
10. The method of claim 1 , wherein the first stress layer and the second stress respectively provides a tensile stress.
11. The method of claim 10 , wherein a total stress of the first stress layer and the second stress layer is about 1 to 50 GPa.
12. The method of claim 10 , wherein a total stress of the first stress layer and the second stress layer is about 1 to 10 GPa.
13. The method of claim 1 , wherein the first stress layer and the second stress respectively provide a compressive stress.
14. The method of claim 13 , wherein a total stress of the first stress layer and the second stress layer is about 0 to −50 GPa.
15. The method of claim 13 , wherein a total stress of the first stress layer and the second stress layer is about 0 to −10 GPa.
16. The method of claim 1 , wherein the at least two metal oxide semiconductor devices are formed as NMOS devices.
17. The method of claim 1 , wherein the at least two metal oxide semiconductor devices are formed as PMOS devices.