Method for manufacturing a semiconductor device capable of preventing the generation of a bridge between a recess gate and a PLC plug

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a screen oxide layer over a surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed;

forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto;

removing the screen oxide film and simultaneously expanding the width of the second recess pattern;

forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along a profile in the second recess pattern;

forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess pattern is not filled;

forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and

removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess pattern.

2. The method according to claim 1 , further comprising:

after forming the screen oxide layer and before forming the first and second recess patterns, performing an ion-implantation process on the semiconductor substrate over which the screen oxide layer is formed.

3. The method according to claim 1 , wherein the step of removing the screen oxide film and simultaneously expanding the width of the second recess pattern is performed through an overetching process.

4. The method according to claim 1 , wherein the step of removing the screen oxide film and simultaneously expanding the width of the second recess pattern is performed so that an interval between the second recess patterns becomes 5 to 20 nm.

5. The method according to claim 1 , wherein the first insulation dielectric layer is formed of an oxide layer.

6. The method according to claim 5 , wherein the oxide layer is formed of a Low Pressure TEOS (LPTEOS) layer.

7. The method according to claim 1 , wherein the first insulation dielectric layer is formed at a thickness of 100 to 300 Å.

8. The method according to claim 1 , wherein the second insulation dielectric layer is formed of an nitride layer.

9. The method according to claim 1 , wherein the second insulation dielectric layer is formed at a thickness of 50 to 200 Å.

10. The method according to claim 1 , wherein the third insulation dielectric layer is formed of an oxide layer.

11. The method according to claim 10 , wherein the third insulation dielectric layer is formed of a sub atmosphere TEOS (SATEOS) layer.

12. The method according to claim 1 , wherein the third insulation dielectric layer is removed through a chemical mechanical polishing (CMP) process.

13. The method according to claim 12 , wherein the CMP process is performed using slurry having removal rate of the nitride layer to the oxide layer being 1:10 to 1:200.

14. The method according to claim 1 , wherein the second insulation dielectric layer is removed through a wet etching process using a phosphate (H 3 PO 4 ) solution.

15. The method according to claim 1 , wherein the first insulation dielectric layer is removed through a wet etching process using a HF or BOE solution.

16. The method according to claim 1 , further comprising:

after the step of removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns, forming a gate dielectric layer over the active region including a surface of the first recess pattern.