Delta checkpoints for a non-volatile memory indirection table

1. A method, comprising:

maintaining an indirection table associated with pages of a non-volatile memory, the indirection table including a mapping of logical-to-physical addresses;

storing a delta checkpoint page in the non-volatile memory, the delta checkpoint page being associated with updates to the indirection table in connection with an erase block of the non-volatile memory, wherein the delta checkpoint page comprises (i) data for the delta checkpoint page, including a logical address for each page in the erase block and (ii) metadata for the delta checkpoint page;

after a power loss event, reading the delta checkpoint page from the non-volatile memory;

re-creating the indirection table based at least in part on the delta checkpoint page; and

arranging to recover a memory state associated with the non-volatile memory in accordance with the re-created indirection table.

2. The method of claim 1 , wherein the non-volatile memory comprises a NAND memory.

3. The method of claim 2 , wherein each page includes user data and metadata, and a plurality of pages comprises the erase block.

4. The method of claim 1 , wherein the data for the delta checkpoint page further includes a bitmask of erased blocks.

5. A method, comprising:

maintaining an indirection table associated with pages of a non-volatile memory, the indirection table including a mapping of logical-to-physical addresses; and

storing a delta checkpoint page in the non-volatile memory, the delta checkpoint page being associated with updates to the indirection table in connection with an erase block of the non-volatile memory, wherein the delta checkpoint page comprises (i) data for the delta checkpoint page, including a logical address for each page in the erase block and (ii) metadata for the delta checkpoint page, wherein the metadata for the delta checkpoint page includes a logical address identifying the page as a delta checkpoint page.

6. A method, comprising:

maintaining an indirection table associated with pages of a non-volatile memory, the indirection table including a mapping of logical-to-physical addresses; and

storing a delta checkpoint page in the non-volatile memory, the delta checkpoint page being associated with updates to the indirection table in connection with an erase block of the non-volatile memory, wherein the delta checkpoint page comprises (i) data for the delta checkpoint page, including a logical address for each page in the erase block and (ii) metadata for the delta checkpoint page, wherein the metadata for the delta checkpoint page includes a master sequence number.

7. The method of claim 3 , wherein the plurality of pages include a number of different erase blocks that represent a virtual erase block.

8. An apparatus, comprising:

an indirection table structure associated with pages of a NAND memory, the indirection table including a mapping of logical-to-physical addresses;

a NAND memory to store a delta checkpoint page, the delta checkpoint page being associated with updates to the indirection table in connection with a plurality of pages comprising an erase block of the NAND memory; and

a recovery apparatus to, after a power loss event;

read the delta information from the NAND memory,

re-create the indirection table based at least in part on the delta checkpoint page, and

arrange to recover a memory state associated with the NAND memory in accordance with the re-created indirection table.

9. An apparatus, comprising:

an indirection table structure associated with pages of a NAND memory, the indirection table including a mapping of logical-to-physical addresses;

a NAND memory to store a delta checkpoint page, the delta checkpoint page being associated with updates to the indirection table in connection with a plurality of pages comprising an erase block of the NAND memory, wherein the delta checkpoint page includes: (i) data for the delta checkpoint page including a logical address for each page in the erase block, and (ii) metadata for the delta checkpoint page, including a logical address identifying the page as a delta checkpoint page and a master sequence number, and further wherein a delta checkpoint entry is to be invalidated when more than one erase block is written to at the same time.