Methods and systems for semiconductor testing using reference dice
View Patent ↗Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.
1. A method of semiconductor testing, comprising:
testing at least one die in a wafer or lot in a current test socket;
while said wafer or lot is being processed in said current test socket and based on data relating to said testing, changing or maintaining workflow related information in order to facilitate adjusting of a test workflow; and
adjusting said test workflow.
2. The method of claim 1 , wherein said test workflow is at least adjusted for a die selected from a group comprising: said at least one tested die, dice in said wafer or lot, dice in a subsequent wafer or lot.
3. The method of claim 1 , wherein each of said at least one tested die had been selected as representative of a group of dice in said wafer or lot that can be assumed to respond similarly to testing, wherein said group includes less than all dice in said wafer or lot, and wherein less than all dice in said group had been selected as representative.
4. The method of claim 1 , wherein said at least one tested die includes less than all dice in said wafer or lot.
5. The method of claim 1 , further comprising:
defining a default test workflow and activation criteria prior to said testing;
wherein if defined activation criteria have been met, said workflow related information is changed or maintained in order to facilitate adjusting of a test workflow from said default test workflow.
6. The method of claim 1 , further comprising:
defining a default test workflow; and
redefining said default test workflow based at least partly on data relating to said testing.
7. The method of claim 1 , wherein said adjusting includes: discarding at least one die.
8. The method of claim 1 , wherein said adjusting includes: retaining at least one die.
9. The method of claim 1 , wherein said adjusting includes referring at least one die for user intervention.
10. The method of claim 1 , wherein said adjusting includes: causing insertion of at least one die into an additional test socket or into an additional sub-step in a test socket.
11. The method of claim 1 , wherein said adjusting includes: repeating a test socket or sub-step in a test socket for at least one die.
12. The method of claim 1 , wherein said adjusting includes: causing omission of inserting at least one die from a test socket or sub-step in a test socket.
13. The method of claim 1 , wherein said adjusting includes: adjusting performance of a subsequent test socket or subsequent sub-step in a test socket.
14. The method of claim 13 , wherein said adjusting performance includes: triggering sampling basis or non-sampling basis for said subsequent test socket or for a subsequent sub-step in a test socket.
15. The method of claim 1 , further comprising: modifying a test flow in said current test socket for at least one die in said wafer or lot in order to facilitate adjusting of said test workflow.
16. The method of claim 1 , wherein said changing or maintaining workflow related information includes: changing or maintaining a value of at least one variable in a test program selected from a group comprising: resort, retest, hold, scrap, and tag.
17. The method of claim 1 , wherein said workflow related information is stored in at least one selected from a group comprising: test program, test database and workflow system.
18. A system for semiconductor testing, comprising:
means for a testing at least one die in a wafer or lot in a current test socket;
means for changing or maintaining workflow related information while said wafer or lot is being processed in said current test socket and based on data relating to said testing, in order to facilitate adjusting of a test workflow; and
means for adjusting said test workflow.
19. The system of claim 18 , further comprising:
means for defining a default test workflow.
20. The system of claim 18 , further comprising: means for storing workflow related information.
21. The system of claim 18 , further comprising:
means for determining a group of semiconductor dice in said wafer or lot which can be assumed to respond similarly to testing, wherein said group includes less than all dice in said wafer or lot, and for selecting at least one representative die from said group wherein said at least one representative die includes less than all dice in said group;
wherein each of said at least one tested die was selected as representative.
22. A computer program product comprising a computer useable medium having computer readable program code embodied therein of semiconductor testing, the computer program product comprising:
computer readable program code for causing the computer to test at least one die in a wafer or lot in a current test socket;
computer readable program code for causing the computer while said wafer or lot is being processed in said current test socket and based on data relating to said testing to change or maintain workflow related information in order to facilitate adjusting of a test workflow; and
computer readable program code for causing the computer to adjust said test workflow.