IP Library › Granted Patent US 7,932,566
Granted Patent B2
US 7,932,566 · App. 12/347,628 · Granted Apr 26, 2011

Structure and system of mixing poly pitch cell design under default poly pitch design rules

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,932,566
App. No.
12/347,628
Granted
Apr 26, 2011
Kind
B2
Abstract

An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.

Claims (35)

1. An integrated circuit comprising:

type-1 cells, the type-1 cells having poly lines with a default poly pitch;

a type-2 cell, the type-2 cell having poly lines with a non-default poly pitch; and

a first boundary region, comprising at least one isolation area in a first direction, between at least one type-1 cell and the type-2 cell, the first boundary region having at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the poly pitch of the type-1 cells and a second portion that complies with the poly pitch of the type-2 cell.

2. The integrated circuit of claim 1 , wherein a width of the type-2 cell is a multiple of the default poly pitch.

3. The integrated circuit of claim 1 further comprising a second dummy poly line within the first boundary region, making all active poly lines in type-1 cells bordering the first boundary region compliant with default poly pitch rules.

4. The integrated circuit of claim 1 , wherein the type-2 cell has the first boundary region on two sides and each of the two sides has a merged dummy poly line.

5. The integrated circuit of claim 1 , further comprising a second boundary region having an expanded isolation area, in a second direction perpendicular to the first direction, between at least one type-1 cell and the type-2 cell, wherein the expanded isolation area is cell height multiplied by default poly pitch.

6. An integrated circuit comprising:

type-1 cells, the type-1 cells having poly lines with a default poly pitch;

a type-2 cell, the type-2 cell having poly lines with a non-default poly pitch; and

a first boundary region, comprising an isolation area, in a first direction, between an at least one type-1 cell and the type-2 cell, the first boundary region having boundary dummy poly lines that comply with the default poly pitch of the type-1 cells.

7. The integrated circuit structure of claim 6 , further comprising a second dummy poly line within the type-2 cell, making active poly lines in type-1 cells bordering the type-2 cell compliant with default poly pitch of the type-1 cells.

8. The integrated circuit structure of claim 6 , wherein a width of the type-2 cell is a multiple of the default poly pitch of the type-1 cells.

9. The integrated circuit structure of claim 6 , further comprising a merged dummy poly line within the type-2 cell that has a first portion complying with the default poly pitch of the type-1 cell and a second portion complying with the non-default poly pitch of the type-2 cell.

10. The integrated circuit structure of claim 6 , further comprising two merged dummy poly lines each dummy poly line having a first portion complying with the default poly pitch of the type-1 cell and a second portion complying with the non-default poly pitch of the type-2 cell.

11. The integrated circuit structure of claim 6 , further comprising a second boundary region having an expanded isolation area, in a second direction perpendicular to the first direction, between poly lines in type-1 cells and poly lines in type-2 cells, wherein the expanded isolation area is cell height multiplied by default poly pitch.

12. A layout system for integrated circuits, the system comprising:

positioning type-1 cells in a device layout, the type-1 cells having a default poly pitch; and

positioning a type-2 cell in the device layout, the type-2 cell having non-default poly pitch, wherein the type-2 cell has a width that is a multiple of the default poly pitch of the type-1 cells.

13. The system of claim 12 further comprising:

placing at least one default poly pitch dummy poly line in an at least one X-direction boundary region between the type-1 cells and the type-2 cell.

14. The system of claim 12 further comprising:

placing at least one merged dummy poly line in an at least one X-direction boundary region between the type-1 cells and the type-2 cell, wherein the at least one merged dummy poly line has a first portion complying with a default poly pitch and a second portion complying with a non-default poly pitch.

15. The system of claim 12 further comprising:

placing a merged dummy poly line in both X-direction boundary regions between the type-1 cells and the type-2 cell, wherein the merged dummy poly line has a first portion complying with a default poly pitch and a second portion complying with a non-default poly pitch.

16. The system of claim 12 further comprising:

increasing an isolation area between the type-1 cells and the type-2 cell in at least one Y-direction boundary region.

17. The system of claim 12 further comprising:

placing default poly pitch dummy poly lines to X-direction boundary regions between the type-1 poly cells and the type-2 poly cell.

18. The system of claim 17 further comprising:

placing default poly pitch dummy poly lines within the type-2 cell.

19. The system of claim 18 further comprising abutting an at least one non-default poly pitch dummy poly line with the default poly pitch dummy poly line.

20. The system of claim 19 further comprising:

merging all abutted dummy poly lines.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2009
From: HOU, YUNG-CHIN; TIEN, LI-CHUN; LU, LEE-CHUNG; LI, PING CHUNG; GUO, TA-PEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 022407/0729 →
Continuity (1)
Related Publication 20100164614A1 · Jul 1, 2010