Row redundancy for content addressable memory having programmable interconnect structure
View Patent ↗A content addressable memory (CAM) device includes an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line, a spare CAM row including a plurality of CAM cells coupled to a spare match line, and row replacement circuitry configured to functionally replace a defective CAM row and each subsequent CAM row in the array with corresponding next adjacent CAM rows, wherein a last CAM row in the array is functionally replaced by the spare CAM row.
1. A content addressable memory (CAM) device, comprising:
an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line;
a spare CAM row including a plurality of CAM cells coupled to a spare match line; and
row replacement circuitry configured to functionally replace a defective CAM row and each subsequent CAM row in the array with corresponding next adjacent CAM rows, wherein a last CAM row in the array is functionally replaced by the spare CAM row, wherein the row replacement circuitry comprises:
a programmable interconnect routing structure (PRS) coupled to the CAM rows and the spare CAM row, the PRS configured to selectively route a match signal from any CAM row as an input match signal to any number of arbitrarily selected CAM rows or spare CAM row at the same time.
2. The CAM device of claim 1 , wherein the PRS comprises inputs coupled to the match lines and to the spare match line.
3. The CAM device of claim 1 , wherein the PRS functionally replaces the defective CAM row with the next adjacent CAM row by re-routing match signals associated with the defective CAM row to the next adjacent CAM row.
4. The CAM device of claim 1 , wherein the PRS disables the defective CAM row by disconnecting the defective CAM row from the PRS.
5. The CAM device of claim 1 , wherein the PRS re-routes match signals associated with each CAM row positioned below the defective CAM row to the corresponding next adjacent CAM row, and re-routes the match signals associated with last CAM row in the array to the spare CAM row.
6. The CAM device of claim 1 , wherein the PRS includes at least one column comprising:
a state signal line; and
a number N of first switching elements, each selectively connecting the state signal line to a corresponding CAM row; and
a second switching element selectively connecting the state signal line to the spare CAM row.
7. A content addressable memory (CAM) device, comprising:
an array having at least one CAM block including a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line;
a spare CAM row including a number of CAM cells coupled to a spare match lines; and
a programmable interconnect routing structure (PRS) coupled to the CAM rows and configured to selectively route a match signal output from any CAM row to any number of other arbitrarily selected CAM rows at the same time, and further configured to functionally replace a defective CAM row with another CAM row in the array.
8. The CAM device of claim 7 , wherein the PRS is configured to functionally replace the defective CAM row with a next adjacent CAM row in the array.
9. The CAM device of claim 8 , wherein the PRS disables the defective CAM row by disconnecting the defective CAM row from the PRS.
10. The CAM device of claim 8 , wherein the PRS is further configured to functionally replace each CAM row in the array positioned below the defective CAM row with the corresponding next adjacent CAM row in the array, and to functionally replace the last CAM row in the array with the spare CAM row.
11. The CAM device of claim 10 , wherein the PRS functionally replaces the defective CAM row with the next adjacent CAM row by re-routing match signals associated with the defective CAM row to the next adjacent CAM row.
12. The CAM device of claim 7 , wherein the PRS includes at least one column comprising:
a state signal line; and
a number N of first switching elements, each selectively connecting the state signal line to a corresponding CAM row; and
a second switching element selectively connecting the state signal line to the spare CAM row.
13. A content addressable memory (CAM) device, comprising:
a plurality of CAM blocks, each CAM block including a number N of CAM rows, and each CAM row including a plurality of CAM cells coupled to a match line;
a spare CAM row including a number of CAM cells coupled to a spare match lines; and
a programmable interconnect routing structure (PRS) coupled to the CAM rows and configured to functionally replace a defective CAM row with another CAM row in the array, wherein the PRS is configured to functionally replace the defective CAM row in a first CAM block with a selected CAM row in a next adjacent CAM block.
14. The CAM device of claim 13 , wherein the PRS is configured to functionally replace a selected CAM row in a last CAM block with the spare CAM row.
15. The CAM device of claim 13 , wherein the PRS functionally replaces the defective CAM row with the selected CAM row in the next adjacent CAM block by re-routing match signals associated with the defective CAM row to the next adjacent CAM block.
16. The CAM device of claim 13 , wherein the PRS disables the defective CAM row by disconnecting the defective CAM row from the PRS.
17. The CAM device of claim 13 , wherein the spare row is positioned after the last CAM row in the last CAM block.
18. The CAM device of claim 13 , wherein the PRS includes a plurality of columns of collinear state signal routing lines, wherein a first column includes a set of state signal lines each having a height of N CAM rows.
19. The CAM device of claim 18 , wherein each set of state signal lines lying within the first column and extending across all the CAM blocks in the corresponding array includes N+1 switching elements.