Thin film transistor, method of manufacturing the same and flat panel display device having the same
A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include a gate electrode formed on a substrate; an active layer made of an oxide semiconductor and insulated from the gate electrode by a gate insulating layer; source and drain electrodes coupled to the active layer; and an interfacial stability layer formed on one or both surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristic as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.
1. A thin film transistor (TFT), comprising:
a substrate;
a gate electrode formed on the substrate;
a gate insulating layer formed on the substrate to cover the gate electrode;
an active layer formed of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;
source and drain electrodes electrically coupled to the active layer; and
an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap of 3.0 to 8.0 eV,
wherein the interfacial stability layer directly contacts at least one of an entire top surface and an entire bottom surface of the active layer.
2. The TFT of claim 1 , wherein the oxide semiconductor comprises zinc oxide (ZnO).
3. The TFT of claim 2 , wherein the oxide semiconductor is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).
4. The TFT of claim 1 , further comprising:
a passivation layer formed on the substrate to cover the active layer, the passivation layer having contact holes formed therein so as to expose the active layer,
wherein the source and drain electrodes are electrically coupled to the active layer through the contact holes.
5. The TFT of claim 1 , wherein sidewalls of the interfacial stability layer and the active layer correspond to each other.
6. The TFT of claim 1 , wherein the interfacial stability layer is formed wider than the active layer when the interfacial stability layer is formed at the bottom surface of the active layer.
7. The TFT of claim 1 , wherein the interfacial stability layer comprises one selected from the group consisting of SiO x , SiN, SiO x N y , SiO x C y , SiO x C y H z , SiO x F y , GeO x , GdO x , AlO x , GaO x , SbO, ZrO x , HfO x , TaO x , YO x , VO x , MgO x , CaO x , BaO x , SrO x , and spin on glass (SOG).
8. The TFT of claim 1 , wherein an oxygen concentration of the interfacial stability layer is 10 19 /cm 3 or lower.
9. A thin film transistor (TFT), comprising:
a substrate;
a gate electrode formed on the substrate;
a gate insulating layer formed on the substrate to cover the gate electrode;
an active layer formed of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;
source and drain electrodes electrically coupled to the active layer; and
an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap equal to or greater than a band gap of the active layer,
wherein the interfacial stability layer directly contacts at least one of an entire to surface and an entire bottom surface of the active layer.
10. A thin film transistor (TFT), comprising:
a substrate;
a gate electrode formed on the substrate;
a gate insulating layer formed on the substrate to cover the gate electrode;
an active layer formed of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;
source and drain electrodes electrically coupled to the active layer; and
an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, an oxygen concentration of the interfacial stability layer being 10 19 /cm 3 or lower,
wherein the interfacial stability layer directly contacts at least one of an entire top surface and an entire bottom surface of the active layer.