High density row RAM for column parallel CMOS image sensors
View Patent ↗A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a single block of memory for storing signals processed by the ADCs. The ADCs process signals received from one group of columns of pixels and, at a different time, the ADCs process signals from another group of columns of pixels. While one of the signals processed from a column is being stored in a first memory bank, signals previously processed and stored in a second memory bank are being readout of the storage locations and provided downstream for further processing.
1. A readout circuit for an imaging device, comprising:
at least one analog-to-digital conversion circuit, each analog-to-digital conversion circuit coupled to receive pixel signals from a plurality of columns of a pixel array; and
a memory coupled to said at least one analog-to-digital conversion circuit having a plurality of memory locations for respectively storing digital signals representing signals on said plurality of columns of said pixel array, at least a first group of said plurality of memory locations being configured to be write-enabled at a time that a second group of said plurality of memory locations is read-enabled, wherein each group of memory locations includes memory locations for each of said plurality of columns and the number of groups of memory locations equal to a number of rows from said columns to be contemporaneously stored.
2. The readout circuit of claim 1 , wherein the first and second groups of memory locations are in first and second memory banks, respectively.
3. The readout circuit of claim 1 , further comprising a ramp signal generator coupled to said at least one analog-to-digital conversion circuit, said generator providing a common ramp comparison signal to each of the at least one analog-to-digital conversion circuits.
4. The readout circuit of claim 3 , wherein said ramp signal generator is configured to provide a digital code signal corresponding to a level of said ramp comparison signal to said plurality of analog-to-digital conversion circuits.
5. The readout circuit of claim 4 , wherein the signal generator is configured to provide digital code signals in parallel to each of said at least one analog-to-digital conversion circuits.
6. The readout circuit of claim 4 , wherein each analog-to-digital conversion circuit further comprises an analog-to-digital comparator for comparing said ramp comparison signal with a signal received from a pixel on a column and for providing a logic signal indicating the results of said comparison.
7. A method of reading out signals from a pixel array, comprising:
selectively coupling an analog-to-digital conversion circuit to and receiving analog pixels signals from a plurality of columns of pixels in a pixel array;
selectively coupling said analog-to-digital conversion circuit to and providing digital representations of said analog pixels signals to a plurality of memory locations in a plurality of memory banks of a memory; and
enabling a memory location in one of said memory banks to be written to at substantially the same time that a memory location from a different memory bank is enabled for read out,
wherein each memory bank includes memory locations for each of said plurality of columns and the number of memory banks is equal to a number of rows from said columns to be contemporaneously stored.
8. The method of claim 7 , wherein each memory bank includes one memory location that is used to write a digital representation from a corresponding column.
9. The method of claim 7 , further comprising converting analog pixel signals to digital representations of said analog pixel signals.
10. The method of claim 9 , wherein said converting comprises the steps of: comparing an analog comparison signal with said analog pixel signals; providing a logic signal indicating the results of said comparing; and synchronizing the storing of a digital value of said comparison signal if said logic signal is true.
11. The method of claim 10 , wherein the analog comparison signal is a common ramp comparison signal.