Semiconductor device and method for manufacturing the same

1. A method for manufacturing a semiconductor device, comprising: forming a trench in a low dielectric constant layer containing carbon formed on a substrate and a first protection insulating layer formed on said low dielectric constant layer,

wherein said forming said trench includes:

forming a resist layer having an opening pattern for forming a trench on said first protection insulating layer, and forming a first concave portion in said first protection insulating layer and said low dielectric constant layer using said resist layer as a mask;

removing a damage layer which is formed on a sidewall of said first concave portion of said low dielectric constant layer when said first concave portion is formed;

forming a second protection insulating layer over the whole surface of said substrate by a chemical vapor deposition technique to form a second concave portion in said first protection insulating layer and said low dielectric constant layer by covering the sidewall of said first concave portion in said first protection insulating layer and said low dielectric constant layer with said second protection insulating layer; and

shaping said second protection insulating layer by etch back so that said trench has a sidewall where said second protection insulating layer is selectively formed on a surface of said low dielectric constant layer.

2. The method according to claim 1 ,

wherein said first protection insulating layer and said second protection insulating layer are exposed at the sidewall of said trench.

3. The method according to claim 1 ,

wherein in said removing said damage layer, the sidewall of said first concave portion has a structure that the surface of said first protection insulating layer protrudes from the surface of said low dielectric constant layer, and in said shaping said second protection insulating layer by etch back, said second protection insulating layer is embedded at the surface of said low dielectric constant layer in an area below said first protection insulating layer.

4. The method according to claim 1 ,

wherein said forming said first concave portion includes removing said resist layer by ashing after forming said first concave portion.

5. The method according to claim 1 ,

wherein said low dielectric constant layer is a SiOC layer or a SiOCH layer.

6. The method according to claim 1 , further comprising, before said forming said trench, forming a via hole which is to be consecutively formed with the trench to constitute a dual damascene trench,

wherein said second protection insulating layer has a relative dielectric constant which is equal to or less than a relative dielectric constant of said low dielectric constant layer.

7. The method according to claim 6 ,

wherein said second protection insulating layer is made of the same material as said low dielectric constant layer.

8. The method according to claim 1 , further comprising, after said forming said trench, forming a via hole which is to be consecutively formed with said trench to constitute a dual damascene trench,

wherein said second protection insulating layer is a SiO 2 layer, a SiOF layer, or a SiOH layer.

9. The method according to claim 1 ,

wherein said second protection insulating layer is a SiO 2 layer, a SiOF layer, a SiOH layer, a SiOC layer, or a SiOCH layer.

10. The method according to claim 1 ,

wherein said low dielectric constant layer is formed on a lower interconnect formed on said substrate, and in said forming said trench, said lower interconnect is exposed when said trench is formed.

11. The method according to claim 1 ,

wherein said first protection insulating layer is a SiO 2 layer.