Circuits and methods for communicating data between domains during voltage and frequency shifting

1. A method for communicating data from a first logic block to a second logic block, the method comprising:

formatting data signals to compensate for propagation delays and different operating frequencies between the first logic block and the second logic block;

changing a signal voltage level of the formatted data signals from an operating voltage of the first logic block to an operating voltage of the second logic block; and

transmitting the formatted and changed data signals from the first logic block to the second logic block via data lines.

2. The method of claim 1 wherein the first logic block is an application controller, a system controller, a processor core, a debug subsystem, an audio subsystem, a video subsystem, an interconnect, a memory unit, or a clock generation unit.

3. The method of claim 1 wherein formatting data signals comprises:

generating source-synchronous signals at the operating frequency of the second logic block to obtain an acceptable skew between signals after the source-synchronous signals are generated.

4. The method of claim 1 wherein formatting data signals comprises generating asynchronous signals that maintain the relative skew between the asynchronous signals, the asynchronous signals controlled by one or more handshake signals between the first and second logic blocks.

5. The method of claim 1 wherein the formatting and changing steps are performed on a third logic block coupled between the first and second logic blocks.

6. The method of claim 1 wherein the integrated circuit is an ASIC.

7. The method of claim 1 wherein the integrated circuit comprises programmable logic blocks.

8. The method of claim 1 wherein changing a signaling voltage level of the formatted data signals occurs on a third logic block distinct from the first and second logic blocks.

9. The method of claim 1 wherein formatting data signals to compensate for the propagation delays and different operating frequencies occurs on the first logic block.

10. A circuit comprising:

a first chiplet configured for an operating voltage and an operating frequency;

a second chiplet configured for a different operating voltage and a different operating frequency, the first and second chiplets communicatively coupled by data paths that exhibit propagation delays;

a data signal formatting circuit arranged to compensate for the propagation delays and different operating frequencies between the first chiplet and the second chiplet, the data signal formatting circuit further arranged to maintain an acceptable skew between formatted data signals; and

a voltage shifting circuit arranged to receive the formatted data signals from the formatting circuit and change a signaling voltage level of the formatted data signals from the operating voltage of the first chiplet to the operating voltage of the second chiplet, such that the changed formatted data signals are conditioned for communication to the second chiplet.

11. The circuit of claim 10 wherein the first and second chiplets each comprise one of an application or system controller, a debug subsystem, an audio subsystem, an SoC interconnect, a memory unit, or a clock generation unit.

12. The circuit of claim 10 wherein the first chiplet and the second chiplet are on different substrates.

13. The circuit of claim 10 wherein the first chiplet and the second chiplet are on the same substrate.

14. The integrated circuit of claim 10 wherein the voltage shifting circuit resides on a third chiplet distinct from the first and second chiplets.

15. The integrated circuit of claim 10 wherein the data signal formatting circuit resides on a transmitting one of the first and second chiplets.

16. An integrated circuit having a first logic block, the first logic block operable at a first clock frequency and a first voltage, and a second logic block, the second logic block operable at a second clock frequency and a second voltage, the first logic block comprising:

a data transforming circuit arranged to transform a set of first data signals compatible with the first logic block into a set of outbound data signals compatible with the second logic block, the outbound set of data signals representative of the first set of data signals and an acceptable level of skew between individual signals of the set of outbound data signals; and

a voltage transforming circuit arranged to transform the set of outbound data signals from the first voltage to the second voltage.

17. The integrated circuit of claim 16 , further comprising:

a clock transforming circuit arranged to generate an outbound clock signal having a frequency that is operationally equivalent to the second clock frequency.

18. The integrated circuit of claim 16 , further comprising:

a finite state machine circuit arranged to handshake request and response signals communicated between the first logic block and the second logic block, the finite state machine further arranged to function in cooperation with the data transforming circuit and the voltage transforming circuit.

19. The integrated circuit of claim 17 wherein the data transforming circuit and the clock transforming circuit have interconnection routing that permits compatible propagation delay of the set of outbound data signals and the outbound clock signal.

20. The integrated circuit of claim 16 wherein the voltage transforming circuit further isolates signals of the first logic block from the second logic block.

21. The integrated circuit of claim 17 wherein the clock transforming circuit is configured to compensate for isolation delays of the voltage transforming circuit.

22. The integrated circuit of claim 16 wherein the voltage transforming circuit resides on a different substrate than the first logic block.

23. The integrated circuit of claim 16 wherein the voltage transforming circuit has a level shifter and a clamp.