Semiconductor storage device and method for producing semiconductor storage device
A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.
1. A semiconductor storage device comprising:
a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation;
an input-signal pad;
a plurality of control-signal pads; and
a switch circuit coupled to at least one of the plurality of control-signal pads, wherein the switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a test mode.
2. The semiconductor storage device according to claim 1 , further comprising:
a control circuit that generates a second control signal,
wherein the switch circuit generates the first control signal based on the second control signal.
3. The semiconductor storage device according to claim 1 , wherein the plurality of control-signal pads include at least one of a DQ-mask-signal pad, a clock-signal pad, a chip-enable-signal pad, a write-enable-signal pad, and an output-enable-signal pad.
4. The semiconductor storage device according to claim 3 , wherein the DQ-mask-signal pad includes a DQ-mask-signal pad for an upper bit side and a DQ-mask-signal pad for a lower bit side.
5. The semiconductor storage device according to claim 1 , wherein the switch circuit generates the first control signal based on a signal from the at least one of the plurality of control-signal pads in a normal mode.
6. The semiconductor storage device according to claim 1 , further comprising:
a control circuit that generates a second control signal based on at least one of an external command and an external signal,
wherein the first control signal is generated based on the signal from the input-signal pad when the second control signal is in a first state,
wherein the first control signal is generated based on a signal from the at least one of the plurality of control-signal pads when the second control signal is a second state.
7. The semiconductor storage device according to claim 1 , wherein the input-signal pad is an address-signal pad.
8. The semiconductor storage device according to claim 2 , further comprising:
an input buffer that determines whether or not to supply a signal from one of the plurality of control-signal pads to an internal circuit based on the second control signal.
9. The semiconductor storage device according to claim 1 ,
wherein the at least one of the plurality of control-signal pads is a clock-signal pad, and
wherein the semiconductor storage device operates based on a clock signal supplied to the input-signal pad.
10. The semiconductor storage device according to claim 1 , further comprising:
a circuit coupled to a control-signal pad other than the at least one of the plurality of control-signal pads,
wherein the circuit generates the first control signal based on a signal from the control-signal pad and supplies the generated first control signal to the timing control circuit.
11. A semiconductor storage device that generates a plurality of control signals for controlling at least one of a read operation and a write operation based on signals from control-signal pads,
wherein a first control signal of the plurality of control signals is generated based on a signal supplied from an input-signal pad in a test mode,
wherein the first control signal is generated based on a signal supplied from a control-signal pad corresponding to the first control signal in a normal mode, and
wherein the first control signal is at least one of a DQ-mask signal, a clock signal, a chip-enable signal, a write-enable signal, and an output-enable signal.
12. The semiconductor storage device according to claim 11 ,
wherein the first control signal is a DQ-mask signal,
wherein a mask operation on a data signal is performed based on the signal supplied from the input-signal pad.
13. The semiconductor storage device according to claim 11 ,
wherein the first control signal is a clock signal,
wherein a clock synchronous operation is performed based on a clock signal supplied from the input-signal pad.
14. The semiconductor storage device according to claim 11 ,
wherein the first control signal is a clock signal,
wherein a clock asynchronous operation is performed based on a signal supplied from the input-signal pad.
15. The semiconductor storage device according to claim 11 , wherein the input-signal pad is an address-signal pad.